参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 122/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
76
Silicon Integrated Systems Corporation
5:4
R/W
CAS# Precharge Time for EDO DRAM
Bits[7:6] Description
00
1T
01
1T during burst cycles, 2T for different cycles.
(One wait state between cycles)
10
2T
11
Reserved
3:2
R/W
CAS# Pulse Width for FP DRAM
Bits[3:2] Description
00
3T
01
2T
10
1T
11
Reserved
1
R/W
CAS# Pulse Width for EDO DRAM
0: 2T
1: 1T
0
R/W
MD to HD Timing Control for EDO/FP Mode DRAM
This bit controls the timing when SiS600 drives the data read from DRAM(MD) onto
HD for CPU memory read cycles. This setting is only effective when CPU read FIFO
is empty and ECC function is disabled. When set to 0, SiS600 will drive MD onto
Host data bus immediately after MD from DRAM is being latched internally. For
some DRAM with slower timing or heavier loading, MD valid time will be lagging
behind and this bit should be set to 1 to insert one wait state.
0: Zero wait state
1: One wait state
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