参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 54/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
14
Silicon Integrated Systems Corporation
4.
PIN ASSIGNMENT
4.1.
SiS600 PIN DESCRIPTION
4.1.1. HOST BUS INTERFACE
NAME
TYPE ATTR
DESCRIPTION
HCLK
I
Host Clock :
Primary clock input drives the part.
ADS#
I/O
GTL+
Address Status :
Address Status is driven by the CPU to indicate the start of a
CPU bus cycle.
HREQ[4:0]#
I/O
GTL+
Request Command:
HREQ[4:0]# are used to define each transaction type during the
clock when ADS# is asserted and the clock after ADS# is
asserted.
BREQ0#
O
GTL+
Symmetric Agent Bus Request:
BREQ0# is driven by the symmetric agent that wants to request
the bus.
BNR#
I/O
GTL+
Block Next Request:
When system is busy, the bus agent can block further transaction
by asserting BNR#.
HLOCK#
I
GTL+
Host Lock :
When CPU asserts HLOCK# to indicate the current bus cycle is
locked.
HIT#
I/O
GTL+
Keeping a Non-Modified Cache Line:
HITM#
I/O
GTL+
Hits a Modified Cache Line:
Hit Modified indicates the snoop cycle hits a modified line in the
L1 cache of CPU.
DEFER#
O
GTL+
Defer Transaction Completion:
SiS600 will use this signal to indicate a retry response to the host
bus.
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