参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 69/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
27
Silicon Integrated Systems Corporation
Note:
1. SiS600 only supports six rows (3 banks) DRAM.
2. It is recommended that board designer must follow DC characteristics of each type DRAM (SDRAM, EDO,
FPM) to design the portion of DRAM in DRAM mode mixed configuration.
5.2.2.
DRAM SCRAMBLE TABLE
The DRAM scramble table contains information for memory address mapping. These tables provide the
translation between CPU host address and memory Row and Column address.
There are several memory address mappings: MA mapping for FPM/EDO DRAM, 2Bank and 4Bank mapping
for SDRAM that SiS600 supports:
5.2.2.1. MA MAPPING TABLE FOR FPM/EDO DRAM
a. Symmetric:
Type
256K (9x9)
1M (10x10)
4M (11x11)
16M (12x12)
Address
Row
Column
Row
Column
Row
Column
Row
Column
MA0
15
3
15
3
15
3
15
3
MA1
16
4
16
4
16
4
16
4
MA2
17
5
17
5
17
5
17
5
MA3
18
6
18
6
18
6
18
6
MA4
19
7
19
7
19
7
19
7
MA5
20
8
20
8
20
8
20
8
MA6
12
9
21
9
21
9
21
9
MA7
13
10
22
10
22
10
22
10
MA8
14
11
14
11
23
11
23
11
MA9
NA
13
12
24
12
24
12
MA10
NA
14
13
25
13
MA11
NA
26
14
b. Asymmetric:
Type
512K (10x9)
1M (11x9)
2M (11x10)
Address
Row
Column
Row
Column
Row
Column
MA0
15
3
15
3
15
3
MA1
16
4
16
4
16
4
MA2
17
5
17
5
17
5
MA3
18
6
18
6
18
6
MA4
19
7
19
7
19
7
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