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参数资料
| 型号： | SIS600 |
| 厂商： | SILICON INTEGRATED SYSTEMS CORP |
| 元件分类： | 外设及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA487 |
| 封装： | BGA-487 |
| 文件页数： | 87/144页 |
| 文件大小： | 1592K |
| 代理商： | SIS600 |
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SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
44
Silicon Integrated Systems Corporation
There are two 64-byte FIFO associated with two IDE channels. The data can be popped into FIFO by the unit of
word or double-word. All accesses to the IDE data port will go through FIFO, no matter prefetch/postwrite is
enabled or not. Accesses to the command or control port will bypass FIFO. This mechanism allows the host to
access command or control ports when FIFO is not empty. The FIFO has an option to be 32-byte in depth(from
Register 52h bit 0 in PCI IDE configuration space), which is for backward compatibility only and is suggested
not to be used. SiS Chip provides the 64-byte FIFO mainly to support Ultra-DMA. Because the Ultra-DMA can
be operated at twice the speed of traditional DMA in mode-2, a small FIFO may easily become bottleneck and
degrade system performance.
The host may need to access command or control ports when
PIO mode or DMA mode data transfer is
undergoing. The IDE controller provides a mechanism to complete the command/control port access without
disrupting the operation of FIFO.
In PIO mode, when doing post write, the command/control port access is held-off until the FIFO is flushed to
IDE. When doing prefetch, the command/control access is held-off until the FIFO is full. Before the
command/control port access is actually carried out, the host will be keep waiting on PCI bus.
In DMA mode, the command/control access will go through a higher priority than the DMA data transfer cycles.
When the command/control access cycle is first seen on the PCI bus, the controller will retry the cycle so that PCI
bus will not be used by the host while it is only waiting. At the same time, the controller will suspend the DMA
data transfer cycles by completing the current cycle successfully, then de-asserts IDACK# to inform IDE device
to stop the DMA data transfer. The IDE device may or may not de-assert its IDREQ at this moment. On the other
hand, the host should keep retrying the command/control cycle on PCI bus. Eventually the cycle will be accepted
and carried out when DMA data transfer is stopped.
After the command/control cycle is completed, the
controller resumes DMA data transfer cycles as soon as the IDE device asserts IDREQ.
Both primary and secondary channels may be programmed as Native mode or Compatibility mode via the Class
Code Field in the controller's Configuration Space register.
In Compatibility mode, the interrupt requests for channel 0 and channel 1 are re-routed to IRQ 14 and IRQ 15 of
the built-in Interrupt Controller.
Following table illustrates the accessing methods to the I/O ports in compatibility mode:
Primary Channel:
Table 5.6-1 Accessing Method to I/O Ports for Primary Channel
READ
WRITE
PORT
ICSA1#
ICSA0#
IIORA#
IIORB#
IIOWA#
IIOWB#
1F0
1
0
1
0
1
1F1
1
0
1
0
1
1F2
1
0
1
0
1
1F3
1
0
1
0
1
1F4
1
0
1
0
1
1F5
1
0
1
0
1
1F6
1
0
1
0
1
1F7
1
0
1
0
1
3F6
0
1
0
1
0
1
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