参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 106/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
61
Silicon Integrated Systems Corporation
BIT
ACCESS
DESCRIPTION
15:10
RO
Reserved
9
R/W
Fast Back-to-Back Enable
This bit controls whether or not the host bridge can do fast back-to-back
transactions to different devices. Please note that even when this bit is disabled, the
host bridge may still do fast back-to-back transactions if the host bridge can
guarantee that the adjacent transactions are destined to the same device. The
register that controls fast back-to-back transactions to the same agent is located in
Register 83h.
0: Disable
1: Enable
8
R/W
SERR# enable
This bit controls the SERR# driver. When this bit is disabled, SiS600 would not
drive SERR# under any condition. When this bit is enabled, SiS600 may drive
SERR# in responding to ECC error or the assertion of ASERR# on A.G.P. bus.
0: Disable
1: Enable
7:3
RO
Reserved
2
RO
Bus Master
Always read as 1.
1
R/W
Memory Space
This bit controls the response to memory space accesses. When the bit is disabled,
the host bridge ignores all access from PCI masters.
0: Disable
1: Enable
0
RO
I/O Space
Default value is 1. The host bridge only respond to the addresses 0CF8h and
0CFCh in the I/O space and the I/O transaction must be generated by the host
bridge itself.
Register 06h
Status
Default Value:
0210h
Access:
Read/Write, Read Only, Write Clear
The Status register is used to record status information for PCI bus related events. Reads to this register behave
normally. Writes are slightly different in that each bit in this register can only be reset(Write Clear from 1 to 0),
but not set. Each bit will be reset whenever the register is written, and the corresponding bit contains “1”. For
instance, to write value 0100_0000_0000_0000b to the register will clear bit 14 and not affect any other bits.
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