参数资料
型号: SIS600
厂商: SILICON INTEGRATED SYSTEMS CORP
元件分类: 外设及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA487
封装: BGA-487
文件页数: 63/144页
文件大小: 1592K
代理商: SIS600
SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
22
Silicon Integrated Systems Corporation
ASERR#
I/O
AGP SERR# :
It is provided for the AGP master to report any error.
AREQ#
I
Request :
AGP master asserts this signal to request the access of the AGP
bus.
AGNT#
O
Grant :
SiS600 grants the AGP bus authority to the AGP bus master to
initiate a bus transaction. Together with ST[2:0], the assertion
of GNT# can also indicates that the master is the recipient of the
previously requested read data, or that the master can provide
write data for a previously enqueued write command.
AAD[31:0]
I/O
AGP/PCI Address/Data Bus :
AC/BE[3:0]#
I/O
AGP/PCI Command/Bye Enables Bus :
APAR
I/O
Parity :
APAR is only used during PCI operation on the AGP bus.
VREF
I
AGP Reference Voltage :
This pin should be guarded by VREFVDD/ VREFVSS on the
motherboard layout.
VREFVDD
PWR
3.3V DC power signal for AGP VREF.
VREFVSS
PWR
Ground signal for AGP VREF.
4.1.6. POWER PINS
NAME
TYPE ATTR
DESCRIPTION
VCC
PWR
+3.3V DC Power Source.
VSS
PWR
Ground signals for core logic.
5VCC
PWR
5V DC Power Source.
AVDD,
AVCC,
AVSS
PWR
Phase Lock Loop circuit Power and Ground.
GTLREF[A:B]
PWR
Reference Voltage for GTL+ interface.
VSSREF[A:B]
PWR
Ground signals for reference voltages.
VTT[A:B]
PWR
Termination to Termination Voltage.
4.1.7. MISC. PINS
NAME
TYPE ATTR
DESCRIPTION
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