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| 型号： | SIS600 |
| 厂商： | SILICON INTEGRATED SYSTEMS CORP |
| 元件分类： | 外设及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA487 |
| 封装： | BGA-487 |
| 文件页数： | 66/144页 |
| 文件大小： | 1592K |
| 代理商： | SIS600 |
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SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
25
Silicon Integrated Systems Corporation
The SiS600 is designed to support Pentium Pro/Pentium II CPU with a 100/66/60 MHz pipeline bus. The host
interface is comprised of a “Fast Host-bus Compliant Block”(FHCB), a “Request Buffering Pool”(RBP), a
“DRAM Pipe”(D-Pipe) and a “PCI Pipe”(P-Pipe). The FHCB is mainly designed for the hand shaking with CPU
and the compliance of the Pentium II host bus protocol. This block can assert the control signals at the fastest
time such that host bus can be pipelined to the most efficient stage. The RBP is capable of buffering eight
consecutive requests, either from CPU or from SiS600 itself. There are two pipes constructed in SiS600 in such a
way that requests from host bus can be serviced concurrently. The first pipe that can call it “DRAM Pipe.” This
pipe is used to pipeline all requests toward onboard DRAM. These requests are arranged close enough that all
DRAM bandwidth are exploited without idle state. The other pipe is named as “PCI Pipe.” This pipe is designed
to service requests toward PCI bus or toward AGP bus. As cycle is executed in “DRAM pipe”, “PCI pipe” is also
optimized to reduce all zero wait state and concurrent execution between CPU-PCI cycles and CPU-AGP cycles.
5.2.
DRAM CONTROLLER
The SiS600 can support up to 1.5GBytes of DRAM and each bank could be single or double sided 72-bit (64-bit
data and 8-bit ECC code) Fast Page Mode (FPM) DRAM, Extended Data Output (EDO) DRAM, and
Synchronous DRAM (SDRAM). The SiS600 supports industry standard SIMM/DIMM modules. Six RAS#/CS#
lines permit up to six rows (3 double sided banks) of DRAM, and mixing the different type of DRAM bank by
bank is acceptable.
The installed EDO/FPM DRAM type can be 256K, 512k, 1M, 2M, 4M, 8M or 16M bit deep by n (n = 4, 8, 16,or
32) bit wide, and both symmetrical and asymmetrical addressing modes are supported. The installed SDRAM
type can be 1M, 2M, 4M, 8M, 16M, 32M bit deep by n (n = 4, 8, 16,or 32) bit wide. The SiS600 DRAM
Controller operates synchronously to the CPU clock.
5.2.1.
DRAM CONFIGURATION
SiS600 supports three banks (double sided DRAM) of DRAM each 64/72-bit wide. The three banks may be
configured in three banks of EDO/FPM SIMM, three banks of EDO/SDRAM DIMM or any other combinations
as required. Access to the banks are not interleaved and need not to be populated starting from row 0 or in
consecutive sequence.
The SiS600 can support EDO, FPM and SDRAM. These different types of DRAM can be mixed for each bank, it
must contain only one type of DRAM in each bank.
The basic configurations are shown as the following sections:
5.2.1.2.
EDO/FPM DRAM CONFIGURATION (4 SIMM/6 SIMM):
EDO/FP
SIMM
MA[11:2]
MA[1:0]
RAMWA#
CAS[7:0]#
RAS1#
RAS0#
MD[63:0]
EDO/FP
SIMM
MA[11:2]
MA[1:0]B
RAMWB#
CAS[7:0]#
RAS3#
RAS2#
MD[63:0]
EDO/FP
SIMM
MA[11:2]
MA[1:0]
RAMWB#
CAS[7:0]#
RAS5#
RAS4#
MD[63:0]
BANK0
BANK1
BANK2
Figure 5.2-1 EDO/FPM DRAM Configuration
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