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参数资料
| 型号： | SIS600 |
| 厂商： | SILICON INTEGRATED SYSTEMS CORP |
| 元件分类： | 外设及接口 |
| 英文描述： | MULTIFUNCTION PERIPHERAL, PBGA487 |
| 封装： | BGA-487 |
| 文件页数： | 80/144页 |
| 文件大小： | 1592K |
| 代理商： | SIS600 |
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SiS600 Pentium II PCI /A.G.P. Chipset
Preliminary V1.0 Jan. 25, 1999
37
Silicon Integrated Systems Corporation
start a transaction on PCI bus, but is reloaded with its initial value whenever the host bus leaves idle state. CIT
actually keeps track on how long the CPU is in idle state. After CIT is expired, the host bridge de-asserts its
request signal just in the same manner as the case of MLT’s expiration.
PGT is a 16-bit timer. MLT and CIT are both 8-bit timers. All of the initial values of the three timers are
programmable and can be tuned according to the nature of the application. Although CIT & MLT are both 8-bit
timers, the initial value of CIT is typically programmed much smaller than MLT.
5.3.2.
PCI BUS INTERFACE
The bridge performs medium address decoding and supports all memory cycles (including memory write,
memory write and invalidate, memory read, memory read multiple and memory read line) and configuration
cycles targeting the bridge.
While the PCI master creating a resource lock on the bridge, the bridge will translate this exclusive access by
keeping the Pentium II bus ownership continuously.
5.3.3.
TARGET INITIATED TERMINATION
In general, the bridge is able to source or sink the data requested by the master until the master terminates the
transaction. But sometimes when the bridge is unable to complete the request, it may use the STOP# signal to
initiate termination of the transaction.
Target retry may occur for one of four reasons.
The bridge cannot meet the initial latency requirement.
The bridge is currently locked by another master.
The posting buffers become unavailable during PCI write.
The posting buffers are not flushed during PCI read.
Disconnect without data may occur for one of two reasons.
The bridge cannot meet the subsequent latency requirement.
The posting buffers become unavailable during PCI write.
Disconnect with data may occur for one of three reasons.
The burst length reaches the resource boundary.
The prefetch is not enabled during PCI read.
The posting buffers become unavailable during PCI write.
5.3.4.
PCI MASTER CONTROLLER (PMR)
PMR locally has 4 level deep 3DW wide circular buffer.
Supports Asynchronous PCI clock.
Supports post write, burst read/write.
Zero wait state burst cycles up to 512 bytes.
Supports fast back-to-back transfer.
Supports PCI LOCK# transaction.
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