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参数资料
| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 18/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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Chapter 2: Getting Started
2–3
Parameterize
3. Under Installed Plug-Ins, expand Interfaces folder and then, click
SerialLite II <version> .
4. Select the output file type for your design; the MegaWizard Plug-In Manager
supports VHDL and Verilog HDL. For this example, select Verilog HDL.
5. The MegaWizard Plug-In Manager shows the project path that you specified in the
New Project Wizard . Append a variation name for the MegaCore function output
files < project path >\< variation name >. For this example, type example as the
variation name.
6. Click Next to display the Parameter Settings page for the SerialLite II MegaCore
function.
Parameterize
This section shows how to parameterize the example SerialLite II MegaCore function
and describes the results of various options. A comprehensive description of all
1
The following parameters are ordered as they appear in the SerialLite II parameter
editor. Not all parameters are supported by, or are relevant for, every MegaCore
function variation.
To parameterize your MegaCore function, follow these steps:
1. Click Parameter Settings in the SerialLite II parameter editor. The Physical Layer
page appears.
2. Enter a data rate in megabits per second (Mbps). The SerialLite II MegaCore
function supports data rates of 622 to 6,375 Mbps per lane.
The data rate must be an acceptable range for the Transfer size . SerialLite II
returns a warning or an error message if you specify a data rate that is not within
the range for the specified Transfer size .
3. Choose a Transfer size . The Transfer size determines the number of contiguous
data columns. The Transfer size also determines the serialization/deserialization
(SERDES) factor and internal data path width:
■
■
■
A Transfer size of 1 equates to an internal data path of 8 bits (Recommended
for less than 2.5 gigabits per second (Gbps))
A Transfer size of 2 equates to an internal data path of 16 bits (Recommended
for less than or equal to 3.125 Gbps)
A Transfer size of 4 equates to an internal data path of 32 bits (Typically for
greater than 3.125 Gbps, and only available for Stratix IV devices)
4. Specify the Reference Clock Frequency . This option defines the frequency of the
reference clock for the Arria II GX or Stratix IV internal transceiver. You can select
any frequency supported by the transceiver. This option is not available in Arria V,
Cyclone V, and Stratix V configurations.
5. Select a Port Type . You have three choices: Bidirectional , Transmitter only , and
Receiver only .
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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