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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 84/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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4–30
Chapter 4: Functional Description
Signals
Table 4–10. Troubleshooting Signals (Part 2 of 2)
Signal
Direction
Clock Domain
Description
Indicates that the receiver regular data port
stat_tc_rdp_thresh_breach
Output
tx_coreclock
FIFO buffer is breached, transmit flow control
link management packet.
Indicates that the receiver priority data port
stat_tc_hpp_thresh_breach
Output
tx_coreclock
FIFO buffer is breached, transmit flow control
link management packet.
Indicates that the transmitter has transmitted
err_tc_roe_rsnd_gt4
Output
tx_coreclock
a segment four times without receiving an
ACK for that segment. The link is restarted.
Retry-on-error only: Indicates that the
stat_tc_roe_timeout
Output
tx_coreclock
transmitter MegaCore function has timed out
waiting for ACK for a packet. The MegaCore
function sends that packet again.
Indicates that the receiver FIFO buffer is still
stat_tc_fc_rdp_retransmit
Output
tx_coreclock
breached, and the refresh timer has reached
maximum. Retransmitting flow control link
management packet (regular data port).
Indicates that the receiver FIFO buffer is still
stat_tc_fc_hpp_retransmit
Output
tx_coreclock
breached, and the refresh timer has reached
maximum. Retransmitting flow control link
management packet (priority data port).
err_tc_is_drop
Output
tx_coreclock
Indicates that irregular segment received
(segment size boundary violation).
Indicates that the link management FIFO
err_tc_lm_fifo_oflw
Output
tx_coreclock
buffer has overflowed. Link management
packets are lost.
Indicates that the receiver to transmitter link
err_rr_rx2txfifo_oflw
Output
rrefclk
management status information FIFO buffer
has overflowed.
stat_rr_fc_rdp_valid
stat_rr_fc_hpp_valid
Output
Output
rrefclk
rrefclk
Indicates that a flow control link management
packet was received (regular data port).
Indicates that a flow control link management
packet was received (priority data port).
Indicates that the RAW FC_TIME value is
embedded in the valid flow control link
stat_rr_fc_value[7:0]
Output
rrefclk
management packet. Decode with the
stat_rr_fc_rdp_valid and
stat_rr_fc_hpp_valid signals.
Indicates that a retry-on-error link
stat_rr_roe_ack
Output
rrefclk
management packet of type ACK was
received.
Indicates that a retry-on-error link
stat_rr_roe_nack
Output
rrefclk
management packet of type NACK was
received.
(1) In broadcast mode, these signals will have the corresponding receiver function number post-fixed. For example, err_rr_crc0 is the CRC error
signal from SerialLite II receiver block 0.
SerialLite II MegaCore Function
User Guide
January 2014 Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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