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参数资料
| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 58/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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4–4
Chapter 4: Functional Description
Clocks and Data Rates
Clocks and Data Rates
A SerialLite II link has two distinct clock rates: the core clock rate and the bit rate. The
core clock rate is the rate of the clock the internal logic is running at. This clock
controls the FPGA logic and is a derived clock from the phase-locked loops (PLLs).
The transmitter and receiver both have their own core clocks, tx_coreclock and
rrefclk respectively.
To determine the clock frequency for tx_coreclock and rrefclk , use the following
formula:
Core clock frequency = Data Rate (Mbps)/(TSIZE×10)
For example, if the data rate is 3,125 Mbps, and the TSIZE is 2, then:
Core clock frequency = 3,125/(2×10) = 156.25 MHz
Aggregate Bandwidth
The bit rate specifies the rate of data transmission on a single lane. In a multilane
configuration, the total available bandwidth is the single-lane bit rate multiplied by
the number of lanes.
For example, calculate the bandwidth for a variation using 8B/10B encoding and an
internal data path of 8 bits (transfer size is equal to 1), and the number of lanes is
equal to 4.
In this mode, the input data bus into the processor portion is 36 bits wide (32 bits of
raw data and 8 bits of control information). With the additional bits per byte (due to
8B/10B encoding) for control information, the data bus size being transmitted from
the byte alignment logic into the protocol-processing portion of the MegaCore
function is equal to the number of lanes × 10 (due to 8B/10B encoding). Thus for 4
lanes, the data bus size is equal to 40 bits (4×10 =40).
For example, a 32-byte packet. Count the number of 32-bit wide rows that are
transmitted into the protocol-processing portion. The result is 8 rows (32 bytes/4
bytes) of solid data, plus one additional row for the start-of-packet marker row and
the end-of-packet marker row (no CRC) which equals 9 rows of 40 bits.
For a 32-byte packet, given a link rate of 800 Mbps × 4 = 3.2 Gbps, the transfer is equal
to the following:
■
■
■
data bits: 256
bits sent: 360
256/360 × 3.2 = 2.276 Gbps
For 64-byte packets, the transfer is the following:
■
■
■
data bits: 512
bits sent: 680
512/680 × 3.2 = 2.409 Gbps
For 128-byte packets, the transfer is the following:
■
■
SerialLite II MegaCore Function
User Guide
data bits: 1,024
bits sent: 1,320
January 2014 Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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