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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 49/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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Chapter 3: Parameter Settings
Transceiver Configuration
The high bandwidth setting provides a faster lock time and tracks more jitter on
the input clock source which passes it through the PLL to help reject noise from the
voltage control oscillator (VCO) and power supplies.
The low bandwidth setting filters out more high frequency input clock jitter, but
increases lock time. The PLL is set to the low setting by default.
The medium setting balances the lock time and noise rejection/jitter filtering
between the high and low settings.
If the number of lanes in the transmit or receive direction is equal to zero, the
bandwidth mode for that direction is disabled. This parameter is also disabled for
Arria II GX devices.
Starting Channel number
The range for the dynamic reconfiguration starting channel number setting is 0 to 380
for Stratix IV GX devices. These ranges are in multiples of four because the dynamic
reconfiguration interface is per transceiver block. The range 0 to 380 is the logical
channel address, based purely on the number of possible transceiver instances. This
parameter is not applicable for Arria II GX devices.
Instantiating a Transceiver Reconfiguration Block
When you use an Arria II GX, Arria V, Cyclone V, Stratix IV, or a Stratix V device, you
can instantiate a transceiver reconfiguration block that dynamically changes the
following physical media attachment (PMA) settings:
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Pre-emphasis
Equalization
V OD
Offset cancelation
1
1
For analog settings, there are no restrictions on using dynamic reconfiguration.
When you use a transceiver-based device, the ALTGX interface allows you to modify
the parameter interface with a reconfiguration block. The altgx_reconfig block is not
instantiated, but the MegaWizard-generated wrapper provides the ports that interface
to the altgx_reconfig block. If you choose to use an altgx_reconfig block, you must
instantiate the altgx_reconfig block and connect the associated signals to the
corresponding SerialLite II MegaCore function top-level signals (tie the
reconfig_fromgxb , reconfig_clk , and reconfig_togxb ports to the altgx_reconfig
block).
You must instantiate the transceiver reconfiguration block on an Arria II GX or a
Stratix IV device, because these device transceivers require offset cancelation. Your
Arria II GX or Stratix IV design can compile without the dynamic reconfiguration
block but it cannot function correctly in hardware.
f For more information about the following topics, refer to the respective documents:
SerialLite II MegaCore Function
User Guide
January 2014 Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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