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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 71/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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Chapter 4: Functional Description
Clocks and Data Rates
Figure 4–16. Transmitter Link Layer
slite2_top
4–17
ctl_txrdp_fth
err_txrdp_ofl w
Regular Data
Port Atlantic
FIFO
slite2_ll
rx2tx_retimer_fifo
Atlantic
Interface
(Reg Data
Packets )
txrdp_clk
txrdp_ena
txrdp_da v
txrdp_sop
txrdp_eop
txrdp_err
txrdp_mty
txrdp_dat
(txrdp_atltop
)
TX Core
Phy Layer
Blocks
txrdp_adr
ctl_txhpp_fth
err_txhpp_ofl w
txhpp_clk
txhpp_ena
High Priority
Port Atlantic
FIFO
(txhpp_atltop)
(Ex xc v r,
slite2_phy)
Atlantic
Interface
(Priority
Packets )
txhpp_da v
txhpp_sop
txhpp_eop
txhpp_err
txhpp_mty
txhpp_dat
txhpp_adr
tx_coreclock
high speed
front end (Phy)
Initialization and Restart
Before the SerialLite II link can operate, the MegaCore function must properly reset
the GX transceiver. The SerialLite II MegaCore function must then be initialized and
trained. The SerialLite II training sequence can generally bring the link up in a few
hundred microseconds; the actual amount of time required varies according to PLL
lock times, the number of lanes, the per-lane deskew, and other variation-specific
factors. The reset of the GX transceiver is controlled by the mreset_n and
gxb_powerdown signals. The minimum pulse width is determined by characterization.
Currently, a 2 ms pulse width is sufficient for the gxb_powerdown input, and three
cycles for the mreset_n signal. For simulation, a reset duration of several clock cycles
(for example, 10) is sufficient.
A link only restarts on its own if a link error occurs during normal operation. A
hardware reset using the mreset_n signal also brings down the link when the reset is
asserted low and reestablishes the link when the reset is released. When one end of
the link is brought down by either of these means, it brings the other end down by
sending training sequences to the other end of the link. The other end of the link
restarts after it sees eight successive training sequences.
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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