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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 82/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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4–28
Chapter 4: Functional Description
Signals
Table 4–9. Protocol Processor’s Error, Status and Control Signals (Part 2 of 2)
Signal
Direction
Clock Domain
Description
Indicates that the Atlantic FIFO buffer has overflowed
err_tc_rxrdp_oflw
Output
tx_coreclock
and data has been lost when Clock compensation is
enabled (regular data port).
Indicates that the Atlantic FIFO buffer has overflowed
err_tc_rxhpp_oflw
Output
tx_coreclock
and data has been lost when the Clock
Compensation is enabled (priority data port).
err_txrdp_oflw
Output
txrdp_clk
Indicates that the Atlantic FIFO buffer has overflowed
and data has been lost (regular data port).
Indicates that the high-priority Atlantic FIFO buffer
has overflowed and data has been lost. If the Retry-
err_txhpp_oflw
Output
txhpp_clk
on-error parameter is turned on, this signal remains
high until the FIFO buffer has been emptied by the
SerialLite II MegaCore function.
stat_rxrdp_empty
stat_rxhpp_empty
Output
Output
rxdrp_clk
rxhpp_clk
Indicates that the internal Atlantic FIFO buffer is
empty, and the read request is ignored.
Indicates that the internal Atlantic FIFO buffer is
empty, and the read request is ignored.
Receive high priority port FIFO threshold low ( dav
[ n -1:0]
ctl_rxhpp_ftl
Input
rxhpp_clk
control). Determines when to inform the user logic
that data is available via the rxhpp_dav signal. This
threshold applies to all buffers. Units are in elements.
Only change at reset.
Receive regular data port FIFO threshold low ( dav
[ n -1:0]
ctl_rxrdp_ftl
Input
rxrdp_clk
control). Determines when to inform the user logic
that space is available via the rxrdp_dav signal. This
threshold applies to all buffers. Units are in elements.
Only change at reset.
Receive high priority port FIFO buffer end-of-packet
(EOP)-based dav control. Assert to turn on dav when
ctl_rxhpp_eopdav
Input
rxhpp_clk
there is an end of packet below the FTL threshold.
Value applies to all Atlantic buffers. Only change at
reset.
Receive regular data port FIFO buffer EOP-based dav
ctl_rxrdp_eopdav
Input
rxrdp_clk
control. Assert to turn on dav when there is an end of
packet below the FTL threshold. Value applies to all
Atlantic buffers. Only change at reset.
[tn-1:0]
[ t n -1:0]
ctl_txhpp_fth
ctl_txrdp_fth
Input
Input
txhpp_clk
txrdp_clk
Transmit high priority port FIFO buffer threshold high
dav control.
Transmit regular data port FIFO buffer threshold high
dav control.
(1) In broadcast mode, these signals will have the corresponding receiver function number post-fixed. For example, err_rr_crc0 is the CRC error
signal from SerialLite II receiver block 0.
(2) n is = FIFO SIZE / ( TSIZE * RX Number of Lanes).
(3) tn is = FIFO SIZE / ( TSIZE * TX Number of Lanes).
SerialLite II MegaCore Function
User Guide
January 2014 Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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