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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 43/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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3–20
Chapter 3: Parameter Settings
Link Layer Configuration
Selecting the Proper Pause Duration
Activation of flow control causes a pause in transmission. You can specify the
duration of this pause in terms of columns. You can specify a pause duration from to 8
to 2,040 columns. In elements, this value is 8/ TSIZE to 2,040/ TSIZE elements. Set the
pause duration based on the rate that your system logic consumes the data received. If
a pause is too long, then overall system bandwidth is reduced. If a pause is too short,
it may have to be renewed, which could result in an overall pause that is too long. Part
of determining the pause duration is the read rate of the RX FIFO.
As an example, assume a theoretical pause needs to be 100 elements long. As a
designer, you would not likely know that at design time, so you must estimate a
reasonable value. The effect of a TSIZE-2 , 120-element pause (240 columns on the
GUI) causes more delay than needed. However, an 80-element delay (160 columns on
the GUI) results in the pause being renewed after 80 elements, for a total 160 elements
of delay, even longer than the 120-element pause.
Selecting the Proper Refresh Value
The flow control refresh period determines the number of columns before a flow
control packet can be retransmitted (for example if a flow control link management
packet is lost or corrupted). This refresh period must be less than the pause quantum
time. The packet is retransmitted if the FIFO buffer is still breached.
The stat_tc_rdp_thresh_breach, stat_tc_hpp_thresh_breach,
stat_fc_hpp_retransmit and stat_tc_fc_hpp_retransmit status signals indicate
whether the refresh period is set appropriately. If stat_tc_rdp_thresh_breach or
stat_tc_hpp_thresh_breach (which indicates that the RX FIFO is still breached) is
still asserted after the FC refresh period (based on the value set), the far transmitter
generates another flow control packet (based on the value set at the Pause Quantum
Time option) and sends it out, causing the stat_fc_hpp_retransmit or
stat_tc_fc_hpp_retransmit to be asserted.
External Flow Control (When RX FIFO Size is 0)
The SerialLite II MegaCore function supports an external flow control when the RX
FIFO size is zero. The rxrdp_dav and rxhpp_dav input signals are provided to activate
flow control to pause the data transmission when the corresponding regular port or
priority data port is selected.
Drive rxrdp_dav low when the fill level of your external FIFO has been breached; this
action triggers the flow control pause request. When this signal is high, no flow
control requests is generated.
Transmit/Receive FIFO Buffers
The transmit FIFO buffers are used by the transmitting end of the SerialLite II link to
store data to be transmitted across the high-speed serial link. The receive FIFO buffers
are used by the receiving end of the SerialLite II link to store data for presentation to
the Atlantic interface and eventual consumption by the system logic.
The SerialLite II MegaCore function automatically sets the width of the receive FIFO
buffers at TSIZE bytes per lane. You specify the buffer size in the SerialLite II
parameter editor.
SerialLite II MegaCore Function
User Guide
January 2014 Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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