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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 76/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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4–22
Chapter 4: Functional Description
Signals
Table 4–4. New Interface Signals
Signal Name
rx_parallel_data_out
rx_coreclk
tx_parallel_data_in
tx_ctrlenable
tx_coreclk
rx_ctrldetect
stat_rr_pattdet
err_rr_disp
flip_polarity
Direction
Input
Input
Output
Output
Input
Output
Input
Input
Output
Width
(Datapath width) x (Number of
receiver channels)
1
(Datapath width) x (Number of
transmitter channels)
(Number of control bits) x
(Number of transmitter
channels)
1
(Number of control bits) x
(Number of receiver channels)
(Number of control bits) x
(Number of receiver channels)
(Number of control bits) x
(Number of receiver channels)
Number of receiver channels
Description
Data input from the hard receiver.
Clock input from the hard receiver.
Data output for the hard transmitter.
Control signal to indicate the control word in
tx_parallel_data_in signal.
Clock input from the hard transmitter.
Control signal to indicate that control word is
detected in the hard transceiver.
Pattern detect output for the hard transceiver.
Disparity error output for the hard transceiver.
Polarity inversion input for the hard transceiver.
Some transceiver signals are removed due to the exclusion of hard transceiver in this
configuration. Refer to the next section for a more detailed description of the signals.
Signals
1
The signals required for a given configuration, as well as the appropriate bus widths,
are created automatically by the SerialLite II parameter editor based upon the
parameter values you select.
Table 4–5. High-Speed Serial Interface Signals (Part 1 of 2)
Signal
Direction
Clock Domain
Description
rxin[ n -1]
Output
—
SerialLite II differential receive data bus. Bus carries
packets, cells, or in-band control words.
txout[ m -1]
Output
—
SerialLite II differential transmit data bus. Bus carries
packets, cells, or in-band control words.
rrefclk
Output
rrefclk
Receive core output PLL-derived clock.
Reference clock used to drive the transmitter PLL. The
trefclk
Input
trefclk
PLL is used to generate the transmit core clock
( tx_coreclock ).
Transmitter core output clock. In Arria II GX and
tx_coreclock
Output
tx_coreclock
Stratix IV designs, the TX PLL output clock and the
primary clock are used for the TX logic.
SerialLite II MegaCore Function
User Guide
January 2014 Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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