参数资料
型号: IPR-SLITE2
厂商: Altera
文件页数: 24/110页
文件大小: 0K
描述: IP SERIALLITE II RENEW
标准包装: 1
系列: *
类型: MegaCore
功能: SerialLite II 协议
许可证: 续用许可证
3. Parameter Settings
Table 3–1 shows the function parameters, which can be set only in the SerialLite II
parameter editor (refer to “Parameterize” on page 2–3 ). The following sections
describe these parameters.
Table 3–1. Default SerialLite II Variation
Parameter
Physical Layer
Device family
Data rate
Transfer size
Reference Clock Frequency
Port Type
Self-Synchronized Link-Up
Default Configuration
Depends on the family specified in the
SerialLite II parameter editor
3,125 megabits per second (Mbps)
2 Columns
156.25 MHz
Bidirectional
Disabled
Number of lanes (Transmitter and Receiver Settings) 1
Scramble/De-Scramble
Broadcast mode
Enable frequency offset tolerance
Link Layer
Data Type
Packet type
Enable flow control
Buffer Size (Transmitter and Receiver)
CRC Generation (Transmitter and Receiver)
Configure Transceiver
Specify Voltage Output Differential (V OD ) control
setting
Specify pre-emphasis control setting
Bandwidth mode (Transmitter and Receiver)
Transmitter Buffer Power (V CCH )
Specify equalizer control setting
Starting channel number
Disabled
Disabled
Disabled
Packets
Data packets
Disabled
1,024 bytes
Disabled
0
0
Low
1.5
0
0
To configure your own variation of the SerialLite II MegaCore function, you must
decide the following issues:
High-level link configuration
Bandwidth required
Whether to use CRC checking
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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