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参数资料
| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 21/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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2–6
1
Chapter 2: Getting Started
Parameterize
c. Select the transmitter and receiver buffer sizes (bytes).
18. If your transmitter or receiver requires cyclic redundancy code (CRC) checking,
turn on the Enable CRC option for your chosen packet type and specify a value
for CRC Type.
19. Click Next .
Set Up Simulation
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL model
produced by the Quartus II software. The model allows for fast functional simulation
of IP using industry-standard VHDL and Verilog HDL simulators.
c You may use these models only for simulation and not for synthesis or any other
purposes. Using these models for synthesis creates a nonfunctional design.
To generate an IP functional simulation model for your MegaCore function, follow
these steps:
1. On the EDA page, under Simulation Libraries , turn on Generate Simulation
Model .
2. Some third-party synthesis tools can use a netlist that contains only the structure
of the MegaCore function, but not detailed logic, to optimize performance of the
design that contains the MegaCore function. If your synthesis tool supports this
feature, turn on Generate netlist .
3. Click Next to display the Summary page.
Generate Files
You can use the check boxes on the Summary page to enable or disable the generation
of specified files. A gray checkmark indicates a file that is automatically generated;
other checkmarks indicate optional files.
To generate your parameterized MegaCore function, follow these steps:
1. Turn on the files you want to generate.
2. To generate the specified files and close the SerialLite II parameter editor, click
Finish . The generation phase can take several minutes to complete.
3. If you generate the MegaCore function instance in a Quartus II project, you are
prompted to add the Quartus II IP File ( .qip ) to the current Quartus II project.
SerialLite II MegaCore Function
User Guide
1
The .qip file is generated by the SerialLite II parameter editor and contains
information about a generated IP core. In most cases, the .qip file contains
all of the necessary assignments and information required to process the
MegaCore or system in the Quartus II compiler. The SerialLite II parameter
editor generates a single .qip file for each MegaCore function.
January 2014 Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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