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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 52/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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Chapter 3: Parameter Settings
Optimizing the Implementation
Table 3–12. Error Summary (Part 2 of 2)
3–29
Error Type
■
Cause
Invalid 8b/10b codes groups
Action
■
■
■
Running disparity errors
Unsupported valid code groups
Link protocol violation
Two possibilities:
■ If Retry-on-error is enabled
and the packet is a priority
Data
■
■
LMP with BIP error
CRC error
packet, request
retransmission.
■
■
■
Unexpected channel number
Out of order packet
Out of order acknowledgment (if retry-
■
Otherwise, mark the packet as
bad and forward it to the user
link layer.
on-error enabled)
Received packet is marked as bad
Packets Marked
Bad
{EBP} marked packet
via the rxrdp_err or rxhpp_err
signals, and forwarded to the
user link layer.
Error signals, such as txrdp_err and txhpp_err , are asserted by user logic. When
txrdp_err is asserted with txrdp_eop , the packet is marked with the end of bad
packet (EBP) marker. The txrdp_err signal is ignored when it is not asserted with
txrdp_eop .
When the txhpp_err is asserted and the Retry-on-error feature is turned off, the
packet is marked with the EBP marker. When the txhpp_err is asserted and the Retry-
on-error feature is turned on, the packet is not transmitted and is silently dropped.
Optimizing the Implementation
There are a number of steps you can take to optimize your design, depending on your
goals. The features selected in your SerialLite II configuration have a substantial
impact on both resource utilization and performance. Because of the number of
different combinations of options that are available, it is difficult to generalize the
performance or resource requirements of a design. In addition, the performance of a
SerialLite II link in isolation is different from the performance of the same link
instantiated alongside large amounts of other logic in the device.
For the most part, the steps you take to improve performance or resource utilization
are similar to the steps you would take for any other design. The following
suggestions are intended to provide ideas, but should not be considered an
exhaustive list.
Improving Performance
Performance is the factor that depends most on what other logic exists in the device. If
the SerialLite II MegaCore function is competing with other logic for routing
resources, inefficient routing could compromise speed. The following sections
describe some things that can be considered if speed is an issue.
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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