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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 48/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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Chapter 3: Parameter Settings
3–25
Transceiver Configuration
This parameter is disabled when the number of lanes in the transmit direction is equal
to zero.
For Stratix IV devices, the pre-emphasis control values supported are 0,1,2,3,4, and 5.
For 0, Pre-emphasis option is turned off. For 1, the pre-emphasis is the maximum
negative value. For 2, pre-emphasis is the medium negative value. The value 3 is a
special value in which only the first post-tap is set (set to the maximum), while the
other taps are off. A value of 4 yields a medium positive value, while 5 sets the pre-
emphasis values to the maximum positive supported values. For Arria II GX devices,
the Pre-emphasis setting cannot be changed.
Transmitter Buffer Power (V CCH )
This setting is for information only and is used to calculate the V OD from the buffer
power supply and the transmitter termination to derive the proper V OD range.
The selections available are 1.5 V for Arria II GX devices.
For Stratix IV devices, the Quartus II software automatically selects 1.4 V or 1.5 V. If
you want to set your preferred V CCH value to the transmit and receive pins, perform
the following steps:
1. In the Quartus II window, on the Assignments menu, click Assignment Editor .
2. In the <<new>> row, in the To column, double-click and type rxin to set value for
the receive pin.
3. Double-click in the Assignments Name column, and click I/O Standard (Accepts
wildcards/groups) . The entry is set to I/O Standard .
4. Double-click in the Value column and click 1.4-V PCML or 1.5-V PCML .
5. In the new <<new>> row, repeat steps 2 to 4 to set the value for the transmit pin
( txout ).
Equalizer Control Settings
The transceiver offers an equalization circuit in each receiver channel to increase noise
margins and help reduce the effects of high frequency losses. The programmable
Equalizer compensates for inter-symbol interference (ISI) and high frequency losses
that distort the signal and reduce the noise margin of the transmission medium by
equalizing the frequency response.
For Stratix IV devices, the equalization control values supported are 0, 1, 2, 3, and 4.
These values correspond to lowest/off (0), between medium and lowest (1), medium
(2), between medium and high (3), and high (4). For Arria II GX devices, the
equalization cannot be changed.
Bandwidth Mode
The transmitter and receiver PLLs in the ALTGX megafunction offer programmable
bandwidth settings. The PLL bandwidth is the measure of its ability to track the input
clock and jitter, determined by the -3 dB frequency of the PLL’s closed-loop gain.
The transmitter offers two settings: high or low . The receiver offers three settings:
high , medium , or low .
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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