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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 77/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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Chapter 4: Functional Description
Signals
Table 4–5. High-Speed Serial Interface Signals (Part 2 of 2)
4–23
Signal
Direction
Clock Domain
Description
Master reset pin, active low. Asserting this signal
causes the entire SerialLite II MegaCore function,
mreset_n
Input
Asynchronous
including the Atlantic FIFO buffers, to be reset.
For Arria V, Cyclone V, and Stratix V designs, hold this
signal asserted until the Custom PHY asserts the
tx_ready and rx_ready output ports.
Force training patterns to be sent. Negate once the
ctrl_tc_force_train
Input
tx_coreclock
receiver has locked. Only used in self-synchronizing
mode. Otherwise, this signal is currently reserved (tie
this signal to 1'b0 ).
stat_tc_pll_locked
Output
tx_coreclock
PLL locked signal. Indicates that the ALTGX PLL has
locked to the trefclk .
stat_rr_link
Output
rrefclk
Link Status. When high, the link is enabled.
(1) n = RX number of lanes
(2) m = TX Number of lanes
(3) In broadcast mode, these signals will have the corresponding receiver function number post-fixed. For example, err_rr_crc0 is the CRC error
signal from SerialLite II receiver block 0.
(4) This signal is removed in configurations targeted for Arria V, Cyclone V, and Stratix V devices due to the exclusion of hard transceivers.
f For more information on Altera gigabit transceiver (ALTGX ) megafunction, refer to
the Arria II GX Transceiver Architecture section in volume 2 of the Arria II GX Device
Handbook , and the Stratix IV Transceiver Architecture section in volume 2 of the
Stratix IV Device Handbook .
Table 4–6. Transceiver Megafunction Signals (Part 1 of 3)
Signal
Direction
Clock Domain
Description
Serial Loopback ( TXOUT internally connected to
ctrl_tc_serial_lpbena
Input
tx_coreclock
RXIN ). Tie signal to 1'b0 to NOT use loopback, tie
to 1'b1 to Use Serial Loopback.
rcvd_clk_out
[ r x n l- 1:0 ]
Output
Per lane recovered clock.
err_rr_8berrdet
[ sr x- 1:0 ]
err_rr_disp
[ sr x- 1:0 ]
Output
Output
rrefclk
rrefclk
8B/10B error detection signal.
Disparity error detection signal
err_rr_pcfifo_uflw
[ r x n l- 1:0 ]
err_rr_pcfifo_oflw
[ r x n l- 1:0 ]
err_rr_rlv
[ r x n l- 1:0 ]
Output
Output
Output
rrefclk
rrefclk
rrefclk
Interface/phase compensation FIFO buffer
underflow signal (Arria II GX and Stratix IV devices
only).
Interface/phase compensation FIFO buffer overflow
signal (Arria II GX and Stratix IV devices only).
Run length violation status signal.
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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