参数资料
型号: IPR-SLITE2
厂商: Altera
文件页数: 7/110页
文件大小: 0K
描述: IP SERIALLITE II RENEW
标准包装: 1
系列: *
类型: MegaCore
功能: SerialLite II 协议
许可证: 续用许可证
1–2
Chapter 1: About This MegaCore Function
Features
Table 1–2 shows the level of support offered by the SerialLite II MegaCore function to
each Altera device family.
Table 1–2. Device Family Support
Device Family
Support
Arria ?
II GX
Final
Arria V
Arria V GZ
Preliminary
Preliminary
Cyclone ?
V
Preliminary
Stratix ?
IV
Final
Features
Stratix V
Other device families
Preliminary
No support
Physical layer features
622 Mbps to 6.375 Gbps per lane
Single or multiple lane support (up to 16 lanes)
8-, 16-, or 32-bit data path per lane
Symmetric, asymmetric, unidirectional/simplex or broadcast mode
Optional payload scrambling
Full-duplex or self-synchronizing link state machine (LSM)
Channel bonding scalable up to 16 lanes
Synchronous or asynchronous operation
Automatic clock rate compensation for asynchronous use
±100 and ±300 parts per million (ppm)
Link layer features
Atlantic ? interface compliant
Support for two user packet types: data packet and priority packet
Optional packet integrity protection using cyclic redundancy code (CRC-32 or
CRC-16)
Optional link management packets
Retry-on-error for priority packets
Individual port (data/priority) flow control
SerialLite II MegaCore Function
User Guide
Unrestricted data and priority packet size
Support for TimeQuest timing analyzer
Polarity reversal
Lane order reversal
January 2014 Altera Corporation
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