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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 89/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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Chapter 5: Testbench
Testbench Specifications
■
■
5–3
The generated data follows a pseudo-random sequence (Verilog HDL) or
incrementing data sequence (VHDL) that is checked by the Atlantic monitors.
Each packet has an incrementing identifier (first byte in the packet) that is checked
by the Atlantic monitor.
The SISTER MegaCore function is a SerialLite II MegaCore function with parameters
derived from the DUT parameters. If the DUT is symmetrical (receiver's parameters
matching transmitter's parameters), the SISTER's parameters match the DUT
parameters. If the DUT is asymmetrical, the SISTER's parameters are different than
the DUT's parameters, so that the DUT's transmitter parameters match the SISTER's
receiver parameters and vice-versa. For a broadcast DUT, there are multiple SISTER
instantiations. Pin monitor utilities monitor the SerialLite II status and error pins of
the DUT and SISTER(s).
1
The Custom PHY IP core is only applicable in configurations targeted for Arria V and
Stratix V devices.
Figure 5–1. SerialLite II Testbench Environment (Non-Broadcast)
SerialLite II Test b ench
Clock and
Reset
Generator
Atlantic
Interface
SerialLite II
High-Speed
Interface
Atlantic
Interface
AGEN_DAT_DUT
AGEN_PRI_DUT
sl2_top
(IP F u nctional
Sim u lation Model)
sl2_top_sister
(IP F u nctional
Sim u lation Model)
AMON_DAT_SIS
AMON_PRI_SIS
AMON_DAT_DUT
AMON_PRI_DUT
DUT
SISTER
AGEN_DAT_SIS
AGEN_PRI_SIS
Stat u s
Stat u s
C u stom
Stat u s
Stat u s
Monitor 1 Monitor X
PHY IP
Monitor 1 Monitor X
(DUT)
(DUT)
Core
(SISTER) (SISTER)
(1) The DUT and the SISTER MegaCore functions may have different parameters; depending on the DUT parameters, and some components may be
missing.
(2) _DAT = Regular Data Port; _PRI = High Priority Port; _DUT = Refers to DUT side; _SIS = Refers to SISTER side.
Depending on the SerialLite II link variation you choose (for example, using the
single, broadcast, or asymmetric mode) the SerialLite II testbench environment may
change, but the basic functionality is unchanged: data is sent or received on the
Atlantic interface of the SerialLite II DUT IP model and received or sent on the
Atlantic interface of the SerialLite II SISTER IP model.
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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