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参数资料
| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 22/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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Chapter 2: Getting Started
2–7
Simulate the Design
4. After your review the generation report, < variation name > .html , in your project
directory, click Exit to close the SerialLite II parameter editor.
Simulate the Design
You can simulate your design using the MegaWizard-generated VHDL and
Verilog HDL IP functional simulation models.
f For more information on IP functional simulation models, refer to the Simulating
Altera also provides a Verilog HDL demonstration testbench that shows you how to
instantiate a model in a design for all configurations. Altera also provides a VHDL
demonstration testbench for a restricted number of configurations. The testbench
stimulates the inputs and checks the outputs of the interfaces of the SerialLite II
MegaCore function, allowing you to evaluate the MegaCore function’s basic
Instantiate the MegaCore
You can now integrate your custom MegaCore function variation into your design
and simulate your complete design using your own custom testbench.
Specify Constraints
This example design applies constraints to create virtual pins and set up timing
analysis.
Assign Virtual Pins
If you are compiling the SerialLite II MegaCore function variation as a standalone
component, you must specify virtual pin assignments. The SerialLite II parameter
editor generates a tool command language (Tcl) script that automates this task. Follow
these steps to run the script:
1. On the Tools menu, click Tcl Scripts to open the Tcl Scripts dialog box.
2. In the project directory, select <variation_name> _constraints .
3. Click Run .
1
The script assumes the default names for the virtual pins. If you have connected the
pins to names other than the default names, you must edit this script and change the
virtual pin names when the core is still compiled in stand-alone mode.
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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