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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 81/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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Chapter 4: Functional Description
Signals
Table 4–7. Atlantic Interface Signals (Part 3 of 3)
4–27
txhpp_err
Signal
Direction
Input
Clock Domain
txhpp_clk
Description
Error indicator on the Atlantic interface.
txhpp_mty[ tm -1:0]
txhpp_dat[ td -1:0]
txhpp_adr[3:0]
Input
Input
Input
txhpp_clk
txhpp_clk
txhpp_clk
Number of empty bytes in the data word.
User data bits.
User-defined packet ID.
(1) In broadcast mode, these signals will have the corresponding receiver function number post-fixed. For example, err_rr_crc0 is the CRC error
signal from SerialLite II receiver block 0.
(2) m is the empty value, which is log2 (data width).
(3) d is the data width, which is 8 × transfer size × the RX number of lanes.
(4) tm is the empty value, which is log2 (data width).
(5) td is the data width, which is 8 × transfer size × the TX number of lanes.
Table 4–8. Atlantic Interface Signals for Streaming Mode
Signal
rxrdp_dat [d-1:0]
Direction
Output
Clock Domain
rrefclk
Description
Received user data bits.
Enable signal on the Atlantic interface.
rxrdp_ena
Output
rrefclk
Indicates that the data is valid on the current clock
cycle.
txrdp_dat [td-1:0]
txrdp_ena
Input
Input
tx_coreclock
tx_coreclock
User data bits to be transmitted.
Enable signal on the Atlantic interface.
Indicates that the data is valid.
Indicates that the core is requesting the user data to
stop while the core inserts the clock compensation
txrdp_dav
Output
tx_coreclock
sequence.
If Clock Compensation is not enabled, this signal will
always be high while the link is up.
(1) In broadcast mode, these signals will have the corresponding receiver function number post-fixed. For example, err_rr_crc0 is the CRC error
signal from SerialLite II receiver block 0.
(2) n is = FIFO SIZE / ( TSIZE * RX Number of Lanes).
(3) tn is = FIFO SIZE / ( TSIZE * TX Number of Lanes).
Table 4–9. Protocol Processor’s Error, Status and Control Signals (Part 1 of 2)
Signal
Direction
Clock Domain
Description
Indicates that the Atlantic FIFO buffer has overflowed
err_rr_rxrdp_oflw
Output
rrefclk
and data has been lost when Clock Compensation is
disabled (regular data port).
Indicates that the Atlantic FIFO buffer has overflowed
err_rr_rxhpp_oflw
Output
rrefclk
and data has been lost when Clock Compensation is
disabled (priority data port).
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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