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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 97/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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Chapter 5: Testbench
Testbench Components Description
If the iptg task is called, idle cycles are inserted between write operations. The
probability of idles between write cycles decreases with larger values of prob .
Table 5–3. iptg Task Field Description
5–11
Field Location
in Task
Field
Valid Values
Description
The prob field sets the probability of a transaction gap. The
1
prob
0 to 0xFFFF_FFFF
(integer)
probability decreases with a larger value of prob .
Before each transaction, a random number between 0 and
prob is generated and compared to prob/2 . If they match,
a random gap is inserted; if not, no gap is inserted.
2
min
0 to 0xFFFF_FFFF
(cycles)
The min field sets the minimum value, in Atlantic clock
cycles, for a random gap between AGEN write transactions.
The max field sets the maximum value, in Atlantic clock
3
max
0 to 0xFFFF_FFFF
(cycles)
cycles, for a random gap between AGEN write transactions.
A max field greater than or equal to the min field is required.
When max==min , no gap occurs.
– verbose(bit_value)
The verbose task enables or disables the display of AGEN verbose messages.
Table 5–4. verbose Task Field Description
Field Location
in Task
Field
Valid Values
Description
Setting bit_value to 1, enables the display of verbose
1
bit_value
1'b0 or 1'b1
messages.
Setting bit_value to 0, disables the display of verbose
messages (default).
– corrupt_sop
The corrupt_sop task corrupts the start of packet (SOP) of the next packet. When
called, it waits for the SOP and corrupts it (makes SOP==0). All the subsequent
packets are not corrupted.
– corrupt_eop
The corrupt_eop task corrupts the end of packet (EOP) of the next packet. When
called, it waits for the EOP and corrupts it (makes EOP==0). All the subsequent
packets are not corrupted.
AGEN Parameters
The MegaWizard Plug-In Manager sets these parameters based on the selected
configuration, and the parameters are fixed for a given SerialLite II configuration.
1
These parameters are documented for reference purposes only. Do not modify them.
– PRIORITY
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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