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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 80/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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4–26
Chapter 4: Functional Description
Signals
Table 4–7. Atlantic Interface Signals (Part 2 of 3)
Signal
Direction
Clock Domain
Description
rxrdp_eop
Output
rxrdp_clk
End of packet indicator on the Atlantic interface.
Error indicator on the Atlantic Interface. This signal is
rxrdp_err
Output
rxrdp_clk
not necessarily held high until rxrdp_eop is
asserted.
rxrdp_mty[ m -1:0]
rxrdp_dat[ d -1:0]
Output
Output
rxrdp_clk
rxrdp_clk
Number of empty bytes in the data word.
User data bits.
rxrdp_adr[7:0]
txrdp_ena
txrdp_dav
txrdp_sop
txrdp_eop
txrdp_err
Output
Input
Output
Input
Input
Input
rxrdp_clk
txrdp_clk
txrdp_clk
txrdp_clk
txrdp_clk
txrdp_clk
User-defined packet ID. Only valid with rxrdp_sop .
Enable signal on the Atlantic interface. Indicates that
the data is valid.
Indicates that the input FIFO buffer is not full.
Start of packet indicator on the Atlantic interface.
End of packet indicator on the Atlantic interface.
Error indicator on the Atlantic interface.
txrdp_mty[ tm -1:0]
txrdp_dat[ td -1:0]
txrdp_adr[7:0]
Input
Input
Input
txrdp_clk
txrdp_clk
txrdp_clk
Number of empty bytes in the data word.
User data bits.
User-defined packet ID.
rxhpp_ena
Input
rxhpp_clk
Enable signal on the Atlantic interface. Indicates that
the data is to be read on the next clock cycle.
Input (No FIFO buffer) determines whether flow
control is required on this port.When this signal is
rxhpp_dav
Input
rxhpp_clk
low, the fill level has been breached. When this signal
is high, the FIFO buffer has enough space for more
words.
Output (With FIFO buffer) represents the buffer’s fill
rxhpp_dav
Output
rxhpp_clk
level. This signal is high when the level is above FTL
or if an EOP is in the buffer.
rxhpp_val
rxhpp_sop
rxhpp_eop
Output
Output
Output
rxhpp_clk
rxhpp_clk
rxhpp_clk
The output data is valid.
Start of packet indicator on the Atlantic interface.
End of packet indicator on the Atlantic interface.
Error indicator on the Atlantic Interface. This signal is
rxhpp_err
Output
rxhpp_clk
not necessarily held high until rxhpp_eop is
asserted.
rxhpp_mty[ m -1:0]
rxhpp_dat[ d -1:0]
Output
Output
rxhpp_clk
rxhpp_clk
Number of empty bytes in the data word.
User data bits.
rxhpp_adr[3:0]
txhpp_ena
txhpp_dav
txhpp_sop
txhpp_eop
Output
Input
Output
Input
Input
rxhpp_clk
txhpp_clk
txhpp_clk
txhpp_clk
txhpp_clk
User-defined packet ID. Only valid with rxhpp_sop .
Enable signal on the Atlantic interface. Indicates that
the data is valid.
Indicates that the input FIFO buffer is not full.
Start of packet indicator on the Atlantic interface.
End of packet indicator on the Atlantic interface.
SerialLite II MegaCore Function
User Guide
January 2014 Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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