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参数资料
| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 74/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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4–20
Chapter 4: Functional Description
MegaCore Configuration for Arria V, Cyclone V, and Stratix V Devices
Testbench
For the SISTER MegaCore function instance, you are required to edit the SerialLite II
MegaCore function dynamically generated testbench to include the Custom PHY IP
core instantiation. The testbench verifies whether the integration of both cores is
functionally correct in the simulation.
f The SISTER MegaCore function is a SerialLite II MegaCore function with parameters
derived from the DUT parameters. For more information about the testbench, refer to
Simulation Support
The Quartus II software generates the simgen netlist, which contains only the
SerialLite II MegaCore function soft logic. The hard transceiver instantiation logic is
not included. You are required to add the Custom PHY IP core simulation files into
the command line Tcl file ( <top level design name>_run_modelsim.tcl ) to enable the
simulation to work in the Modelsim simulator.
f For more information about the compilation and simulation flow, refer to the design
Parameter Settings For SerialLite II MegaCore and Custom PHY IP Core
The parameters associated with the transceiver configuration ( Configure Transceiver
page) in the SerialLite II MegaCore function are disabled since there is no hard
transceiver in this configuration. Other parameters for the SerialLite II MegaCore
for a more detailed description of the parameters.
The SerialLite II MegaCore function requires specific features to be enabled on the
Custom PHY IP core to support this configuration. Table 4–3 list the options that you
can set using the Custom PHY IP core parameter editor in the MegaWizard Plug-In
Manager. Note that the required ports are essential for the Custom PHY IP core
instantiation.
Table 4–3. Custom PHY IP Core Settings (Part 1 of 2)
Option
pll_locked output port
tx_ready output port
rx_ready output port
Enable TX Bitslip
Create rx_coreclkin port
Description
Provides Tx PLL locking status in the Custom PHY IP core.
Indicates that the Custom PHY IP core is ready to transmit data.
Indicates that the Custom PHY IP core is ready to receive data.
Provides control for bitslip functionality.
Provides transceiver clock output to the rx_coreclk signal in the
SerialLite II MegaCore.
For Arria V, Cyclone V, and Stratix V designs with more than 1
channel, connect transceiver PHY rx_clkout(0) to
rx_coreclkin (N-1:0) .
Setting
Optional
Required
Required
Off
Required
SerialLite II MegaCore Function
User Guide
January 2014 Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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