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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 79/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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Chapter 4: Functional Description
Signals
Table 4–6. Transceiver Megafunction Signals (Part 3 of 3)
4–25
Signal
(1) , (2)
Direction
Clock Domain
Description
Transceiver block reset and power down. This
signal resets and powers down all circuits in the
transceiver block. This does not affect the refclk
buffers and reference clock lines. All the
gxb_powerdown
Input
—
gxb_powerdown input signals of cores placed in
the same transceiver block should be tied
together.The gxb_powerdown signal should be tied
low or should remain asserted for at least 2ms
whenever it is asserted.
(1) rxnl is the receive number of lanes; txnl is the transmit number of lanes.
(2) srx is the transfer size × the receive number of lanes.
(3) recon_quad is the total number of Quads being used.
(4) If the altgx_reconfig block is not used, the signal will not toggle (set to a fixed value) and thus is not on any clock domain. If the
altgx_reconfig block is used, this signal is on the reconfig_clk domain.
(5) This signal is removed in configurations targeted for Arria V and Stratix V devices due to the exclusion of hard transceivers.
1
1
These signals are only present when the Link Layer mode is enabled and the Atlantic
FIFO buffer is used.
There are no specific requirements for Atlantic clocks ( rxrdp_clk , rxhpp_clk ,
txrdp_clk and txhpp_clk ) as they are all system dependent. The Atlantic clocks at the
read side must be fast enough to prevent backpressure which decreases bandwidth
efficiency.
Table 4–7. Atlantic Interface Signals (Part 1 of 3)
Signal
Direction
Clock Domain
Description
rxrdp_clk
txrdp_clk
rxhpp_clk
txhpp_clk
rxrdp_ena
Input
Input
Input
Input
Input
—
—
—
—
rxrdp_clk
Atlantic receive regular data port clock.
Atlantic transmit regular data port clock.
Atlantic receive high priority port clock.
Atlantic transmit high priority port clock.
Enable signal on the Atlantic interface. Indicates that
the data is to be read on the next clock cycle.
Input (No FIFO buffer) determines whether flow
control is required on this port. When this signal is
rxrdp_dav
Input
rxrdp_clk
low, the fill level has been breached. When this signal
is high, the FIFO buffer has enough space for more
words.
Output (With FIFO buffer) represents the buffer’s fill
rxrdp_dav
Output
rxrdp_clk
level. This signal is high when the level is above FTL
or if an EOP is in the buffer.
rxrdp_val
rxrdp_sop
January 2014
Altera Corporation
Output
Output
rxrdp_clk
rxrdp_clk
The output data is valid.
Start of packet indicator on the Atlantic interface.
SerialLite II MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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