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参数资料
| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 92/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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5–6
Chapter 5: Testbench
Simulation Flow
Running a Simulation
Altera provides a ModelSim simulation script that allows you to run a simulation
based on the simulation configuration you have chosen. To run the simulation while
in the ModelSim Tcl environment, first ensure that you have set the Quartus II project
directory to be the working directory.
1. Run ModelSim ( vsim ) to bring up the user interface.
2. Execute the simulation run, by typing the appropriate command:
do <variation name>_run_modelsim.tcl (Verilog HDL)
or
do <variation_name>_run_modelsim_vhdl.tcl (VHDL)
The testbench creates the run_modelsim.log file as an output file.
1
If you select Arria V or Stratix V as the target device family, you are required to add a
list of the Custom PHY IP core simulation files into the command line Tcl file. For
Simulation Pass and Fail Conditions
The meaning of pass or fail can vary based on intent, so this section clarifies what it
means when a simulation run ends and failure is reported.
The execution of a simulation run consists of the following components:
■
■
■
■
Create data to be transported through the link
Verify that the data arrived with or without errors
Verify that the various protocols were honored in the delivery of the data
Confirm that the state of the link is consistent
The testbench concludes by checking that all of the packets have been received. In
addition, it checks that the Atlantic packet receivers ( amon modules) have not detected
any errors in the received packets.
If no errors are detected, and all packets are received, the testbench issues a message
stating that the simulation was successful.
If errors were detected, a message states that the testbench has failed. If not all packets
have been detected, the testbench eventually times out (time limit set by
WATCHTIME), which causes an error and the testbench to fail.
In summary, the testbench checks the following:
■
■
■
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SerialLite II MegaCore Function
User Guide
Were all expected stimulus generated?
Did all expected packets arrive and was the data error-free?
If errors occurred on the data, did the SerialLite II logic detect the errors?
Were there any protocol errors?
Is there any evidence of the simulation running too long out of control?
January 2014 Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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