参数资料
型号: IPR-SLITE2
厂商: Altera
文件页数: 93/110页
文件大小: 0K
描述: IP SERIALLITE II RENEW
标准包装: 1
系列: *
类型: MegaCore
功能: SerialLite II 协议
许可证: 续用许可证
Chapter 5: Testbench
5–7
Simulation Flow
If any of those checks detect a problem, the simulation is reported as failing. In a
correctly operating testbench, the only reason for failing is the detection of
deliberately inserted errors. There is a distinction between a simulation run failing
and a test failing. If you insert errors and the errors are detected, the simulation fails.
However, the test was successful because the errors were detected. For this reason,
simulation failure is not by itself an indication of a problem. Example 5–1 shows the
ModelSim log for a successful run.
Example 5–1. run_modelsim.log (Part 1 of 2)
********************************************************************************
#CORE DUT : Comming out of RESET
# Note : CMU PLL is reset
# Time: 0 ns Instance: tb.slite2_top_sis.nlOiO1O.m_cdr.m_rxpll
# Note : CMU PLL is reset
# Time: 0 ns Instance: tb.slite2_top_dut.n1il1i.m_cdr.m_rxpll
# 0 ns VERIFY 0 of 1: example_tb
# ******************************************************************************
# CORE DUT : In RESET
# ******************************************************************************
# ******************************************************************************
# CORE SIS : In RESET
# ******************************************************************************
# Note : CMU PLL is reset
# Time: 2 ns Instance: tb.slite2_top_dut.n1il1O
# Note : CMU PLL is reset
# Time: 2 ns Instance: tb.slite2_top_sis.nlOiO0l
# ******************************************************************************
# CORE DUT : Comming out of RESET
# ******************************************************************************
# ******************************************************************************
# CORE SIS : Comming out of RESET
# ******************************************************************************
# Reset DONE = 1
# **************************
# ******* Link is up. ******
# **************************
# Linked Up, Utils ON
# AGEN_DAT_DUT 4: sent packet id=0 addr=0x14 size=268 err=1, time: 7276 ns
# AGEN_DAT_SIS 11: sent packet id=0 addr=0x9b size=282 err=0, time: 7428 ns
# AGEN_DAT_DUT 6: sent packet id=0 addr=0xe6 size=293 err=1, time: 7434 ns
# AGEN_DAT_DUT 7: sent packet id=0 addr=0xf7 size=379 err=1, time: 8176 ns
# AGEN_DAT_DUT 2: sent packet id=0 addr=0x62 size=373 err=1, time: 8244 ns
# AGEN_DAT_DUT 13: sent packet id=0 addr=0xdd size=446 err=0, time: 8402 ns
# AMON_DAT_SIS: Received ALL 5 packets, time: 13290 ns
# AGEN_DAT_SIS 5: sent packet id=0 addr=0xd5 size=645 err=1, time: 15328 ns
# AGEN_DAT_SIS 15: sent packet id=0 addr=0x0f size=678 err=0, time: 16059 ns
# AGEN_DAT_SIS 8: sent packet id=0 addr=0x98 size=848 err=0, time: 18330 ns
# AGEN_DAT_SIS 4: sent packet id=0 addr=0xa4 size=916 err=1, time: 18686 ns
# AMON_DAT_SIS: Received ALL 5 packets, time: 13290 ns
# AGEN_DAT_SIS 5: sent packet id=0 addr=0xd5 size=645 err=1, time: 15328 ns
# AGEN_DAT_SIS 15: sent packet id=0 addr=0x0f size=678 err=0, time: 16059 ns
# AGEN_DAT_SIS 8: sent packet id=0 addr=0x98 size=848 err=0, time: 18330 ns
# AGEN_DAT_SIS 4: sent packet id=0 addr=0xa4 size=916 err=1, time: 18686 ns
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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参数描述
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IPR-TRIETHERNET 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IPR-TRIETHERNETF 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors
IP-R-UNIV-CORE 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA