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参数资料
型号： IPR-SLITE2
厂商： Altera
文件页数： 73/110页
文件大小： 0K
描述： IP SERIALLITE II RENEW
标准包装： 1
系列： *
类型： MegaCore
功能： SerialLite II 协议
许可证： 续用许可证
Chapter 4: Functional Description
4–19
MegaCore Configuration for Arria V, Cyclone V, and Stratix V Devices
MegaCore Configuration for Arria V, Cyclone V, and Stratix V Devices
The supported features for the SerialLite II MegaCore function in Arria V, Cyclone V,
and Stratix V devices are the same with the Stratix IV GX devices except for the hard
transceiver features. Since there is no hard transceiver in this configuration, you need
to instantiate the Custom PHY IP core and integrate both cores in your design. You
can find the Custom PHY IP core in the following directory in the MegaWizard
Plug-In Manager: Installed Plug-Ins > Interfaces > Transceiver PHY > Custom PHY
<version> .
Table 4–2 lists the Custom PHY IP core blocks and the respective data rate that the
SerialLite II MegaCore function utilizes for this configuration.
Table 4–2. Custom PHY IP Core Blocks and Data Rate Used by SerialLite II MegaCore Function
FPGA Fabric
Transceiver
Interface
Width
Blocks Enabled
Data Rate (Mbps)
for Arria V GZ/
Arria V GX/
Stratix V
Data Rate (Mbps)
for Cyclone V
Word alignment mode: Manual (1) /Automatic synchronization state
32
(TSIZE = 4)
machine (2)
Word alignment pattern: 10'h17c
3,126 to 6,375
3,126 to 5,000
8B/10B encoder/decoder
16
(TSIZE = 2)
8
(TSIZE = 1)
Word alignment mode: Automatic synchronization state machine
Word alignment pattern: 10'h17c
8B/10B encoder/decoder
Word alignment mode: Automatic synchronization state machine
Word alignment pattern: 10'h17c
8B/10B encoder/decoder
1,000 to 5,000
622 to 2,500
1,000 to 3,750
622 to 1,875
Notes to Table 4–2 :
(1) Assert the rx_enapatternalign register in Custom PHY through the Avalon-MM interface to trigger another
alignment when synchronization is lost.
(2) Applicable only for Arria V GZ and Stratix V devices.
f For more information about the Custom PHY IP core, refer to the Altera Transceiver
PHY IP Core User Guide .
Design Consideration
When you instantiate the SerialLite II MegaCore function and Custom PHY IP core,
you must apply the following considerations to create a working design.
Compilation
If you use Tcl constraints to make assignments for the SerialLite II MegaCore function,
you must perform the following actions:
■
■
Identify the Custom PHY IP core clock node
Set the Custom PHY IP core reference clock frequency accordingly in the .sdc file
for design integration between the SerialLite II MegaCore function and Custom
PHY IP core
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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