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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 83/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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Chapter 4: Functional Description
4–29
Signals
be connected to external logic. In general, they are for diagnostic purposes. Some
signals in Table 4–10 are only available in certain configurations.
Table 4–10. Troubleshooting Signals (Part 1 of 2)
Signal
Direction
Clock Domain
Description
Reset controller logic Done signal. When
stat_tc_rst_done
Output
tx_coreclock
high, the reset controller has completed the
ALTGXB reset sequence successfully.
err_rr_foffre_oflw
Output
rrefclk
Indicates that frequency offset tolerance FIFO
buffer has overflowed. The link restarts.
Indicates that frequency offset tolerance FIFO
buffer has underflowed. The link does not go
stat_tc_foffre_empty
Output
tx_coreclock
down. IDLE characters are inserted. This
does not have a negative impact on the core,
and is simply for diagnostic purposes.
stat_rr_ebprx
Output
rrefclk
Indicates that an end of bad packet character
was received.
err_rr_bip8
Output
rrefclk
Indicates that a BIP-8 error was detected in
the received link management packet.
err_rr_crc
Output
rrefclk
Indicates that a CRC error was detected in the
received segment/packet.
Indicates that a flow control link management
err_rr_fcrx_bne
Output
rrefclk
packet was received, but flow control is not
enabled.
Indicates that a retry-on-error link
err_rr_roerx_bne
Output
rrefclk
management packet was received, but Retry-
on-error parameter is not enabled.
err_rr_invalid_lmprx
Output
rrefclk
Indicates that an invalid link management
packet was received.
err_rr_missing_start_dcw
Output
rrefclk
Indicates that data byte(s) received, but a
start of data control word (DCW) is missing.
Indicates that the start and end address fields
err_addr_mismatch
Output
rrefclk
do not match. Segments are marked with an
error. Possible packets are destined for an
invalid address.
May indicate catastrophic error. Polarity on
the input ALTGXB lines is reversed; the
MegaCore function cannot operate.
err_rr_pol_rev_required
Output
rrefclk
If you see the signal for the first time, you
should manually reset the core. If the signal
triggers again after you reset, then it
confirms a catastrophic error.
err_rr_dskfifo_oflw
Output
rrefclk
Indicates that deskew FIFO buffer has
overflowed. Link restarts.
Indicates that a bad column was received
stat_rr_dskw_done_bc
Output
rrefclk
after successful deskew completion. Link is
restarted.
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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