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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 51/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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3–28
Chapter 3: Parameter Settings
Error Handling
Table 3–11. ALTGX Support Signals
Signal
reconfig_fromgxb
gxb_powerdown
I/O
O
I
Description
The reconfig_fromgxb output signal is driven to an external dynamic
reconfiguration block. The width of this bus depends on the number of lanes (it may
require multiple transceiver QUAD blocks), and the device family (for Arria II GX and
Stratix IV, the bus is wider due to offset cancelation support).
This signal identifies the transceiver channel whose settings are being transmitted to
the dynamic reconfiguration. This signal must be connected as described in the
A rr ia II GX Device Ha n dbook or the S t r atix IV Device Ha n dbook if the external dynamic
reconfiguration block is used. Otherwise, leave this signal unconnected.
For Arria II GX and Stratix IV, you must use the dynamic reconfiguration block because
they require offset cancelation.
gxb_powerdown resets and powers down all circuits in the transceiver block. This
signal does not affect the refclk buffers and reference clock lines.
All the gxb_powerdown input signals of cores placed in the same quad should be tied
together. The gxb_powerdown signal should be tied low or should remain asserted for
at least 2 ms whenever it is asserted.
Error Handling
The SerialLite II MegaCore function does error checking and has an interface to view
local errors. The errors are categorized, and the effect of an error depends on the type
of error that occurs.
The SerialLite II MegaCore function has three error types:
■
■
■
Data error
Link error
Catastrophic error
Table 3–12. Error Summary (Part 1 of 2)
Error Type
Cause
Action
Catastrophic
■
■
■
LSM cannot reverse polarity
LSM cannot reorder lanes
Eight consecutive {|TS1|} sequences
SerialLite II enters
nonrecoverable state
received in all lanes simultaneously
■
■
Loss of character alignment
Loss of lane alignment
Link
■
Loss of characters from
Trigger link initialization
underflow/overflow
SerialLite II MegaCore Function
User Guide
■
■
Data error threshold exceeded
Retry-on-error timer expired three
times
January 2014 Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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