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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 8/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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Chapter 1: About This MegaCore Function
General Description
1–3
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■
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
Support for OpenCore ? Plus evaluation
General Description
The SerialLite II MegaCore function is a simple, high-speed, low-latency, and
low-resource point-to-point serial data communication link.
The MegaCore function performs up to the following rates:
■
■
■
3.75 Gbps in Arria II GX devices
5 Gbps in Cyclone V devices
6.375 Gbps in Stratix IV, Arria V, and Stratix V devices
The SerialLite II MegaCore function is highly configurable, and provides a wide range
of functionality suited to moving data in many different environments.
The SerialLite II MegaCore function provides a simple and lightweight way to move
data from one point to another reliably at high speeds. It consists of a serial link of up
to 16 bonded lanes, with logic to provide a number of basic and optional link support
functions. The Atlantic interface is the primary access for delivering and receiving
data.
The SerialLite II protocol specifies a link that is simple to build, uses as little logic as
possible, and requires little work for a logic designer to implement. The SerialLite II
MegaCore function uses all of the features available in the SerialLite II protocol. You
can parameterize the MegaCore function using the SerialLite II parameter editor.
A link built using the SerialLite II MegaCore function operates at 622 Mbps to 6.375
Gbps per lane. Link reliability is enhanced by the 8B10B encoding scheme and
optional CRC capabilities. You can achieve further reductions in the bit-error rate by
using the optional retry-on-error feature. Data rate and consumption mismatches can
be accommodated using the optional flow-control feature to ensure that no data is
lost.
blocks: a protocol processing portion (data link layer) and a high-speed front end
(physical layer).
Figure 1–1. SerialLite II MegaCore Function High-Level Block Diagram
One or More
Lanes
You can use the SerialLite II MegaCore function in the following applications:
■
Chip-to-chip connectivity
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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