- 您现在的位置：买卖IC网 > PDF目录16076 > IPR-SLITE2 (Altera)IP SERIALLITE II RENEW PDF资料下载
参数资料
| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 53/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页当前第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页
3–30
Chapter 3: Parameter Settings
Optimizing the Implementation
Feature Selection
The following features impact speed more significantly. Your system may require
some of these, but if any are optional or can be reconsidered, this may help your
performance. Before making any changes, verify that the feature you want to change
is in the critical speed path.
■
■
■
Lane count—running more lanes more slowly reduces the operating frequency
required (but uses more logic resources).
CRC—the CRC generation and checking logic degrades performance and latency.
In particular, if you are using CRC-32, evaluate carefully whether the extra
protection over CRC-16 is really worthwhile, because CRC-16 has less impact on
speed.
Receive FIFO buffer size—large FIFO buffers increase fanout and may require
longer routing to extend further inside the device.
Running Different Seeds
If your first attempt at hitting performance is close to the required frequency, try
running different placement seeds. This technique often yields a better result. For
information on seed specification and improving speed, you can refer to the
Command-Line Scripting and the Design Space Explorer chapters in volume 2 of the
Quartus II Handbook respectively.
Limiting Fanout
Depending on the number of lanes and the size of memories you choose, fanout can
impact performance. Limiting the fanout during synthesis causes replication of high-
fanout signals, improving speed. If high-fanout signals are the critical path, limiting
the fanout allowed can help. Refer to volume 1 of the Quartus II Handbook for more
information on limiting fanout.
Floorplanning
The SerialLite II MegaCore function does not come with any placement constraints.
The critical paths depend on where the Fitter places SerialLite II logic in the device, as
well as the other logic in the device. You can use standard floorplanning techniques to
improve performance. Refer to volume 2 of the Quartus II Handbook for more
information on floorplanning.
Minimizing Logic Utilization
The amount of logic required for a SerialLite II link depends heavily on the features
you choose.
The following features have a significant impact on logic usage:
■
■
SerialLite II MegaCore Function
User Guide
Lane count—running fewer lanes at higher bit rates, if possible, uses less logic (but
places more of a burden on meeting performance).
CRC—significant savings can be made by eliminating CRC, or in particular,
moving from CRC-32 to CRC-16 in high-lane-count designs. If you are using CRC-
32, evaluate carefully whether the extra protection over CRC-16 is really
worthwhile, because CRC-16 uses far fewer resources.
January 2014 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| EBM28DRMN-S288 | CONN EDGECARD 56POS .156 EXTEND |
| RSM08DTKI-S288 | CONN EDGECARD 16POS .156 EXTEND |
| ECM06DTMD-S273 | CONN EDGECARD 12POS R/A .156 SLD |
| ECM06DTMN-S273 | CONN EDGECARD 12POS R/A .156 SLD |
| RBM12DCCI-S189 | CONN EDGECARD 24POS R/A .156 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
发布紧急采购，3分钟左右您将得到回复。