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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 47/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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3–24
Chapter 3: Parameter Settings
Transceiver Configuration
Transceiver Configuration
This section describes the optional, configurable Altera ALTGX gigabit transceiver
megafunctions. The transceiver megafunction offers several configuration options
that can be set based on board-level conditions, design constraints, or other
application-specific requirements, to ensure the proper operation of the serial link.
1
If you select Arria V or Stratix V as the target device family, you are required to
instantiate the Custom PHY IP core as the hard transceiver. For more information
f For more information on Altera gigabit transceiver (ALTGX ) megafunction, refer to
the Arria II GX Transceiver Architecture section in volume 2 of the Arria II GX Device
Handbook , and the Stratix IV Transceiver Architecture section in volume 2 of the
Stratix IV Device Handbook .
Voltage Output Differential (V OD ) Control Settings
The Stratix IV transceivers allow you to set the V OD to handle different length,
backplane, and receiver requirements. A range from 200 to 1,200 mV is supported for
Stratix IV devices. Arria II GX devices have a fixed value, which cannot be changed.
The range is decoded using the GUI integer value and the on-chip transmitter
programmable termination values.
Table 3–10 shows how the V OD value you chose in the SerialLite II parameter editor
corresponds to the mV value. The V OD value is 0 by default.
Table 3–10. V OD Control Settings
V OD Value (Per Lane)
0
1
2
3
4
5
6
7
100 Ohms (mV) Stratix IV
200
400
600
700
800
900
1,000
1,200
This parameter is disabled when the number of lanes in the transmit direction is equal
to zero.
Pre-Emphasis Control Settings
The programmable Pre-emphasis setting boosts the high frequencies in the transmit
data signal, which may be attenuated by the transmission medium. The Pre-emphasis
setting maximizes the data eye opening at the far-end receiver, which is particularly
useful in lossy transmission mediums. Specify pre-emphasis control setting
parameter is set to 0 by default.
SerialLite II MegaCore Function
User Guide
January 2014 Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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