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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 50/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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Chapter 3: Parameter Settings
Transceiver Configuration
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3–27
Dynamic reconfiguration and offset cancellation for Arria II GX devices, refer to
Dynamic reconfiguration and offset cancellation for Stratix IV devices, refer to the
Dynamic reconfiguration and using the Altera Reconfiguration Controller for
ALTGX Support Signals
This section describes the ALTGX support signals, which are only present on variants
that use the Arria II GX and Stratix IV integrated PHY. They are connected directly to
the ALTGX instance. In many cases these signals must be shared with ALTGX
instances that are implemented in the same device. The following signals exist:
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cal_blk_clk
reconfig_clk
reconfig_togxb
reconfig_fromgxb
gxb_powerdown
Table 3–11. ALTGX Support Signals
Signal
cal_blk_clk
reconfig_clk
reconfig_togxb
I/O
I
I
I
Description
The cal_blk_clk input signal is connected to the ALTGX calibration block clock
( cal_blk_clk ) input. All instances of ALTGX in the same device must have their
cal_blk_clk inputs connected to the same signal because there is only one
calibration block per device. This input should be connected to a clock operating as
The reconfig_clk input signal is the ALTGX dynamic reconfiguration clock. This
signal must be connected as described in the A rr ia II GX Device Ha n dbook or the
Otherwise, this signal must be set to 1'b0 .
The reconfig_togxb [ N :0] input signal is driven from an external dynamic
reconfiguration block. The signal supports the selection of multiple transceiver
channels for dynamic reconfiguration. This signal must be connected as described in
the A rr ia II GX Device Ha n dbook or the S t r atix IV Device Ha n dbook if the external
dynamic reconfiguration block is used. Otherwise, you must set this signal to
4'b0010 for Arria II GX and Stratix IV devices.
N value is 3 for Arria II GX and Stratix IV devices.
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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相关代理商/技术参数 |
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| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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