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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 27/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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3–4
■
Chapter 3: Parameter Settings
Physical Layer Configuration
If you select a reference clock frequency that is not equal to the
data rate/(transfer size) * 10, the Clock Compensation option is disabled if the
Receiver only port type option is turned on.
Port Type
The Port Type parameter offers three options: Bidirectional , Transmitter only , and
Receiver only . If you turn on the Bidirectional option, you must specify values for
Transmitter Settings and Receiver Settings . Under Transmitter Settings , you need to
specify the Number of lanes , and select whether or not to enable the Scramble and
Broadcast mode . Under Receiver Settings , you must specify the settings for the
Number of lanes , and select whether or not to enable the De-Scramble option. If you
turn on Transmitter only option, you must specify values for Transmitter Settings
only , and if you turn on Receiver only option, you must specify values for Receiver
Settings only.
The Number of lanes parameter dictates the number of serial links, essentially the
number of external inputs and outputs (I/Os) for the MegaCore function.
If you set the Number of lanes for the transmitter and receiver settings to the same
value, you configure the MegaCore function to operate in symmetric, bidirectional
If you set the Port Type to Receiver only or Transmitter only , you configure the
MegaCore function to operate in unidirectional mode, transmitter, or receiver only.
If you set the Port Type to Bidirectional , but have the number of lanes set to a value
other than zero, but not equal to the other function’s value, you configure the
MegaCore function to operate in asymmetric mode. Refer to Figure 3–6 and
Figure 3–2. Symmetric Mode Block Diagram
FPGA 1
One or more lanes
( u p to N)
FPGA 2
Atlantic
Interface
Light-weight
Linklayer
PHY
Layer
CDR
SERDES
CDR
SERDES
PHY
Layer
Light-weight
Linklayer
Atlantic
Interface
One or more lanes
( u p to N)
(1) A full line indicates a mandatory lane.
(2) A dashed line indicates an optional lane.
SerialLite II MegaCore Function
User Guide
January 2014 Altera Corporation
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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