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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 57/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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Chapter 4: Functional Description
4–3
Interface Overview
On the transmitter side, the user input data packets are sent to the Atlantic interface
once the txrdp_ena signal is asserted ( txrdp_ena pin is level triggered). The data
packets go through several internal processes in the SerialLite II data link layer and
physical layer, including all packet framing, CRC, and 8B/10B generation, and bit
serializing. These internal processes produce some core latency of approximately 21
clock cycles to finally send the packets to the High Speed Serial Interface (HSSI) link.
The latency calculation is based on the tx_coreclock frequency and is counted from
the first data presented at the Atlantic interface on the transmitter side to the first data
that appeared at the HSSI.
On the receiver side, the data packets are transmitted through the HSSI link and go
through another SerialLite II MegaCore function. In the other SerialLite II MegaCore
function, the same reverse processes are done in the SerialLite II data link layer and
physical layer to strip off the framing and return the raw data back in the Atlantic
interface. The data are presented at the Atlantic interface after approximately 25 clock
cycles of latency. The latency is counted from the first data that appeared at the HSSI
to the first data that reaches the Atlantic interface on the receiver side.
1
However, these latencies are based on the simulations and parameters set in the
testbench. The latencies vary depending on different designs and implementations,
and the fill levels of the Atlantic FIFO buffer in designs where the fill levels are used.
High-Speed Serial Interface
The high-speed serial interface always appears at the external device pins. The high-
speed interface consists of the differential signals that carry the high-speed data
Figure 4–3. High-Speed Serial Interface Connections
SerialLite II
MegaCore
Function
( N ear)
txout
rxin
rxin
txout
SerialLite II
MegaCore
Function
(Remote)
High- S peed S e r ial I n te r face
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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