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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 32/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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Chapter 3: Parameter Settings
3–9
Physical Layer Configuration
Scramble
Scrambling the data eliminates repeating characters, which affect the EMI
substantially at high data rates. A linear feedback shift register (LSFR) is used as a
pseudo-random number generator to scramble the data, using the following
polynomial equation:
G(x) = X 16 + X 5 + X 4 + X 3 + 1
The transmitted bits are XOR ed with the output of the LFSR in the data stream. At the
receiver, the data stream is again XOR ed with an identical scrambler to recover the
original bits. To synchronize the transmitter to the receiver, the COM character
initializes the LFSR with the initial seed of 0×FFFF XOR ed with the lane number (LN).
Scrambling is recommended for data rates greater than 3,125 Mbps, and is optional
for lower data rates (622 to 3,125 Mbps inclusive). This parameter applies only to the
transmitter, and allows for scrambling (like CRC) to be enabled in one direction only,
as required.
De-Scramble
This parameter applies only to the receiver, and allows for descrambling (like CRC) to
be enabled in one direction only, as required. Descrambling is required if the incoming
data stream is scrambled.
Broadcast Mode
If you enable the broadcast mode parameter for the transmitter, you configure the
MegaCore function to use a single shared transmitter and multiple receivers in the
master device, as shown in Figure 3–8 and Figure 3–9 . The number of receivers is
determined by the number of lanes chosen for the slave receiver. The master
transmitter uses its output lanes to broadcast identical messages to all slave receivers,
and each slave responds individually by sharing the master's lanes.
Figure 3–8. Broadcast Mode Block Diagram
Master FPGA
TX Tsvr 1
Broadcastmessage
Slave FPGA N
Shared TX
Link
Shared TX
PHY
TX Tsvr 2
TX Tsvr N
Broadcastmessage
Broadcastmessage
Atlantic
Interface
RX Link 1
RX Link 2
RX Link N
RX PHY 1
RX PHY 2
RX PHY N
RX Tsvr 1
RX Tsvr 2
RX Tsvr N
CDR
SERDES
PHY
Layer
Light-weight
Linklayer
Atlantic
Interface
N-ret u rn
lanes
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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