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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 34/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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Chapter 3: Parameter Settings
3–11
Link Layer Configuration
Lane Order
It is possible that the order of lanes may be incorrect due to layout errors. It may also
be reversed, with the most significant lane of one end of the link connected to the least
significant lane of the other end, due to layout constraints. The SerialLite II logic
always detects a lane order mismatch, and compensates for the reversed lane order on
the receive side. This reversal occurs during link initialization and remains in place for
as long as the link is active.
The SerialLite II logic only corrects reversed lane order. If the lane order is scrambled,
the receiving end cannot unscramble it. The following example shows a possible four-
lane system, where Serial Lite II can reverse the four-lane system:
Example 3–1. SerialLite II Lane Reversal
Lane
Lane
Lane
Lane
0
1
2
3
->
->
->
->
Lane
Lane
Lane
Lane
3
2
1
0
Frequency Offset Tolerance
The Enable frequency offset tolerance parameter sets the value for the frequency
offset tolerance (clock compensation). This parameter also determines whether the
system is configured for synchronous or asynchronous clocking operation. If you
enable this parameter, the values available are ±100 ppm and ±300 ppm.
Link Layer Configuration
This section describes the options available to parameterize the link layer of the
SerialLite II MegaCore function variation.
Data Type:Packets
Packet mode for packet-based protocols. The data port expects data to arrive in
packets, marked by asserting start of packet (SOP) at the beginning and end of packet
(EOP) at the end of the packet. The receiver passes these packets to the user logic via
the Atlantic interface, with the packet boundaries marked by SOP and EOP.
Data Type:Streaming
The regular data port allows data to be formatted as a stream or in packets. Streaming
data has no beginning or end. It acts like an infinite-length packet and represents an
unending sequence of data bytes. The only Atlantic signals present are txrdp_ena ,
txrdp_dav , and txrdp_dat (valid and data) in the transmitter, and rxrdp_ena and
rxrdp_dat for a receiver instantiation. There is no backpressure for the receiver
function; consequently, the user logic must accept the data when rxrdp_ena is high.
There is only backpressure in the transmitter function if clock compensation is
enabled ( txrdp_dav is negated when the clock compensation sequence is inserted).
Once system link up is complete, your logic should provide data continuously. The
SerialLite II MegaCore function does not encapsulate streaming data. Streaming
mode does not include link-layer functions.
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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