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| 型号： | IPR-SLITE2 |
| 厂商： | Altera |
| 文件页数： | 40/110页 |
| 文件大小： | 0K |
| 描述： | IP SERIALLITE II RENEW |
| 标准包装： | 1 |
| 系列： | * |
| 类型： | MegaCore |
| 功能： | SerialLite II 协议 |
| 许可证： | 续用许可证 |
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Chapter 3: Parameter Settings
3–17
Link Layer Configuration
When flow control is enabled, the SerialLite II MegaCore logic monitors the triggering
receive FIFO buffer and, when a threshold is reached, issues a pause instruction. It
takes some time for the pause instruction to be issued, traverse the connection, and for
transmission to be stopped. It takes more time for all the data that has already been
transmitted to be stored in the receive FIFO buffer. Therefore, there must be a certain
amount of space left in the receive FIFO buffer above the threshold to hold the data
that arrives during this delay. This headroom has contributions from the core latency
If the far receive FIFO buffer is still in breach of the threshold when the flow control
refresh period timer expires, the far receiver automatically renews the pause to extend
the flow control period. This renewal occurs until the fill level of far receive FIFO is no
longer greater than the threshold. When the renewed flow control packet reaches the
near transmitter before the current pause expires, the pause time is refreshed.
■
■
This refresh time must be set so that the renewed flow control packets are received
by the near transmitter before the current pause time completes. Set the value of
Refresh period to be smaller than Pause quantum time in the Priority Packet
Settings or Data Packet Settings section on the Link Layer page.
If the refresh period is small, more flow control packets are sent on the link,
possibly degrading the performance of an alternate active port. This is a trade off
for the link bandwidth performance.
To overcome head-of-line blocking, every port has its own flow control that suspends
the flow of data to either the priority port or the regular data port, depending on the
FIFO buffer status. For example, if the near transmitter receives a flow control pause
request for the priority port, the data on the regular port is transmitted (as long as the
regular port is not also being requested to pause).
January 2014
Altera Corporation
SerialLite II MegaCore Function
User Guide
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相关代理商/技术参数 |
参数描述 |
|---|---|
| IPR-SRAM/QDRII | 功能描述:开发软件 QDRII SRAM Control MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-SSIP | 功能描述:开发软件 Crypto Bundle BU Solution RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNET | 功能描述:开发软件 Triple Speed Ethernt MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IPR-TRIETHERNETF | 功能描述:开发软件 3x Spd Ethernet MAC MegaCore RENEWAL RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| IP-R-UNIV-CORE | 制造商:Brady Corporation 功能描述:UNIVERSAL RIBBON CORE; For Use With:Bradys IP Printer ;RoHS Compliant: NA |
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