参数资料
型号: IPR-SLITE2
厂商: Altera
文件页数: 64/110页
文件大小: 0K
描述: IP SERIALLITE II RENEW
标准包装: 1
系列: *
类型: MegaCore
功能: SerialLite II 协议
许可证: 续用许可证
4–10
Chapter 4: Functional Description
Clocks and Data Rates
Figure 4–9. No Receiver FIFO Buffers No Frequency Offset Clock Structure
rc v d_clk_out[n-1:0] (1)
slite2_top
Atlantic
rrefclk
rc v d_clk0
Regular
(rrefclk
domain)
Atlantic
Priority
(rrefclk
RX Core
W ord Aligner (&
Training Pattern
Detection),
[Link State
Machine]
n-bit
PComp_FIFO_0*
PComp_FIFO_n-1
Byte
deserializer
Byte
#n SLITE2
High
Speed
Links
domain)
n-bit
deserializer
rc v d_clkn-1
RREFCLK
Atlantic
Regular
txrdp_clk
ATLFIFO
tx_coreclock
tx_coreclock
Training
n-bit
Byte
serializer
#m SLITE2
Generator [Link
State Machine]
High
Speed
TX Core
Byte
Links
tx_coreclock
n-bit
serializer
Atlantic
Priority
txhpp_clk
ATLFIFO
TXPLL
XCVR
Reset Sync
tx_coreclock
Note to Figure 4–9 :
(1) Individual recovered clocks (one per channel).
SerialLite II MegaCore Function
User Guide
mreset_n
trefclk
January 2014 Altera Corporation
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