19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
19-5
When the parity function is enabled, the parity mode should be selected using UPMD/USI_UCFGx register.
Setting UPMD to 0 (default) adds a parity bit and checks for odd parity. Setting UPMD to 1 adds a parity bit
and checks for even parity.
Sampling clock
UCHLN = 0, UPREN = 0, USTPB = 0
UCHLN = 0, UPREN = 1, USTPB = 0
UCHLN = 0, UPREN = 0, USTPB = 1
UCHLN = 0, UPREN = 1, USTPB = 1
UCHLN = 1, UPREN = 0, USTPB = 0
UCHLN = 1, UPREN = 1, USTPB = 0
UCHLN = 1, UPREN = 0, USTPB = 1
UCHLN = 1, UPREN = 1, USTPB = 1
s1
D0
D1
D2
D3
D4
D5
D6
s2
s1
D0
D1
D2
D3
D4
D5
D6
p
s2
s1
D0
D1
D2
D3
D4
D5
D6
s2
s3
s1
D0
D1
D2
D3
D4
D5
D6
p
s2
s3
s1
D0
D1
D2
D3
D4
D5
D6
D7
s2
s1
D0
D1
D2
D3
D4
D5
D6
D7
p
s2
s1
D0
D1
D2
D3
D4
D5
D6
D7
s2
s3
s1
D0
D1
D2
D3
D4
D5
D6
D7
p
s2
s3
s1: start bit, s2 & s3: stop bit, p: parity bit
4.4.1 Transfer Data Format in UART Mode (LSB first)
Figure 19.
Settings for SPI Master Mode
19.4.5
When the USI is used in SPI master mode, configure the SPI clock polarity/phase, clock mode, and data length.
Also enable/disable the receive data mask function.
SPI clock polarity and phase settings
Use SCPOL/USI_SCFGx register to select the SPI clock polarity. Setting SCPOL to 1 treats the SPI clock as
active low. Setting it to 0 (default) treats it as active high.
The SPI clock phase can be selected using SCPHA/USI_SCFGx register.
These control bits set transfer timing as shown in Figure 19.4.5.1.
US_SCKx (SCPOL = 1, SCPHA = 1)
US_SCKx (SCPOL = 1, SCPHA = 0)
US_SCKx (SCPOL = 0, SCPHA = 1)
US_SCKx (SCPOL = 0, SCPHA = 0)
US_SDIx/US_SDOx
Fetching received data
into shift register
D7 (MSB)
D0 (LSB)
4.5.1 Clock and Data Transfer Timing (MSB first)
Figure 19.
Clock mode
Either normal or fast clock mode can be selected using SFSTMOD/USI_SCFGx register. Setting SFSTMOD to
0 (default) places the USI into normal mode and the USI generates the transfer clock by dividing the T16F out-
put by 2. Setting SFSTMOD to 1 places the USI into fast mode and the USI uses PCLK supplied from the CLG
directly as the transfer clock. The fast mode does not use the T16F.
Data length
The data length can be selected using SCHLN/USI_SCFGx register. Setting SCHLN to 0 (default) configures
the data length to 8 bits.
Setting SCHLN to 1 configures the data length to 9 bits. In 9-bit mode, 8-bit data is prefixed with a command
bit (1 bit). The command bit is used for controlling the SPI LCD controller connected to the USI. The command
bit value to be transmitted can be specified using SCMD/USI_SCFGx register. Setting SCMD to 1 configures
the command bit to high. Setting SCMD to 0 configures the command bit to low.