19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
19-8
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
The STDIF flag indicates the transmit data buffer status. STDIF is set to 1 indicating that the transmit data buf-
fer becomes empty when data written to the transmit data buffer is sent to the transmit shift register. STDIF is
an interrupt flag. An interrupt request can be generated when this flag is set to 1 (see Section 19.7). Write sub-
sequent data to the transmit data buffer to start the following transmission using this interrupt. The transmit data
buffer size is 1 byte, but a shift register is provided separately to allow data to be written while the previous
data is being sent. If an interrupt is not used for transmission, be sure to confirm that the transmit data buffer is
empty before writing transmit data. Writing data before STDIF has been set will overwrite earlier transmit data
inside the transmit data buffer.
In SPI master mode, the SSIF flag indicates the shift register status. This flag switches to 1 when transmit data
is loaded from the transmit data buffer to the shift register and reverts to 0 once the data is sent. Read this flag
to check whether the SPI controller is operating or at standby.
spi_sck
TD[7:0]
Shift register
US_SCKx pin
(SCPOL = 0, SCPHA = 1)
US_SCKx pin
(SCPOL = 0, SCPHA = 0)
US_SDOx pin
SSIF
STDIF
Interrupt
AD7
AD6
AD5
AD4
AD3
AD2
AD1
BD5
BD4
BD3
BD2
BD1
AD0
BD0
Write
Transmit buffer empty interrupt
Reset by writing 1
Transmit buffer empty interrupt
(MSB first)
Data A
Data B
BD7
BD6
5.2.1 Data Transmission Timing Chart (SPI master mode)
Figure 19.
Data reception
Write dummy data to the transmit data buffer. Writing to the transmit data buffer creates the trigger for recep-
tion as well as transmission start. Writing actual transmit data enables simultaneous transmission and reception.
This starts the SPI clock output from the US_SCKx pin.
The data is received in sequence in the shift register at the SPI clock edge (see Figure 19.4.5.1). The received
data is loaded into the receive data buffer once the 8 bits of data are received in the shift register.
The received data in the buffer can be read from RD[7:0]/USI_RDx register.
The SPI controller includes two status flags for transfer control: SRDIF/USI_SIFx register and SSIF/USI_SIFx
register.
The SRDIF flag indicates the receive data buffer status. This flag is set to 1 when the data received in the shift
register is loaded into the receive data buffer, indicating that the received data can be read out. SRDIF is an
interrupt flag. An interrupt request can be generated when this flag is set to 1 (see Section 19.7). Read the re-
ceived data from the receive data buffer using this interrupt. The receive data buffer size is 1 byte, therefore the
received data must be read before the subsequent data reception has completed. Furthermore, SRDIF must be
reset by writing 1. If the subsequent receive data is written to the receive data buffer when SRDIF is 1, an over-
run error occurs.
The SSIF flag indicates the shift register status. This flag switches to 1 at the beginning of data reception and
reverts to 0 once the data is received. Read this flag to check whether the SPI controller is operating or at stand-
by.