19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
19-28
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
US_SCKx (SCPOL = 1, SCPHA = 1)
US_SCKx (SCPOL = 1, SCPHA = 0)
US_SCKx (SCPOL = 0, SCPHA = 1)
US_SCKx (SCPOL = 0, SCPHA = 0)
US_SDIx/US_SDOx
Fetching received data
into shift register
D7 (MSB)
D0 (LSB)
8.2 Clock and Data Transfer Timing
Figure 19.
D1
SMSKEN: Receive Data Mask Enable Bit
Enables the receive data mask function.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Setting SMSKEN to 1 enables the receive data mask function. When the receive data mask function is
enabled, the USI transmits the data stored in the transmit data buffer repeatedly until the slave device
sends back a value other than the mask data set to SMSK[7:0]/USI_SMSKx register. In this case, the
transmit buffer empty and receive data buffer full interrupt flags are not set and no interrupt is generated.
For normal data transfer, set SMSKEN to 0 (default) to disable the receive data mask function.
D0
SFSTMOD: Fast Mode Select Bit
Selects Fast mode.
1 (R/W): Fast mode
0 (R/W): Normal mode (default)
Either normal or fast clock mode can be selected using SFSTMOD. Setting SFSTMOD to 0 (default)
places the USI into normal mode and the USI generates the transfer clock by dividing the T16F output
by 2. Setting SFSTMOD to 1 places the USI into fast mode and the USI uses PCLK supplied from the
CLG directly as the transfer clock. The fast mode does not use the T16F.
USI Ch.x SPI Master Mode Interrupt Enable Registers (USI_SIEx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Ch.x SPI
Master Mode
Interrupt
Enable Register
(USI_SIEx)
0x50c7
0x50e7
(8 bits)
D7–3 –
reserved
–
0 when being read.
D2
SEIE
Receive error interrupt enable
1 Enable
0 Disable
0
R/W
D1
SRDIE
Receive buffer full interrupt enable 1 Enable
0 Disable
0
R/W
D0
STDIE
Transmit buffer empty int. enable
1 Enable
0 Disable
0
R/W
Note: This register is effective only in SPI master mode. Configure the USI channel to SPI master mode
before this register can be used.
D[7:3]
Reserved
D2
SEIE: Receive Error Interrupt Enable Bit
Enables interrupt requests to the ITC when an overrun error occurs.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set this bit to 1 to process overrun errors using interrupts.
D1
SRDIE: Receive Buffer Full Interrupt Enable Bit
Enables interrupt requests to the ITC when received data is loaded to the receive data buffer.
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set this bit to 1 to read received data using interrupts.