![](http://datasheet.mmic.net.cn/120000/S1C17564F00E10C_datasheet_3574343/S1C17564F00E10C_216.png)
19 UNIVERSAL SERIAL INTERFACE (USI) [S1C17564]
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
19-29
D0
STDIE: Transmit Buffer Empty Interrupt Enable Bit
Enables interrupt requests to the ITC when data written to the transmit data buffer is sent to the shift
register (i.e. when data transmission begins).
1 (R/W): Enabled
0 (R/W): Disabled (default)
Set this bit to 1 to write data to the transmit data buffer using interrupts.
USI Ch.x SPI Master Mode Interrupt Flag Registers (USI_SIFx)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
USI Ch.x SPI
Master Mode
Interrupt Flag
Register
(USI_SIFx)
0x50c8
0x50e8
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3
SSIF
Transfer busy flag
1 Busy
0 Idle
0
R
D2
SEIF
Overrun error flag
1 Error
0 Normal
0
R/W Reset by writing 1.
D1
SRDIF
Receive buffer full flag
1 Full
0 Not full
0
R/W
D0
STDIF
Transmit buffer empty flag
1 Empty
0 Not empty
0
R/W
Note: This register is effective only in SPI master mode. Configure the USI channel to SPI master mode
before this register can be used.
D[7:4]
Reserved
D3
SSIF: Transfer Busy Flag Bit
Indicates the SPI transfer status.
1 (R):
Operating
0 (R):
Standby (default)
SSIF is set to 1 when the SPI starts data transfer in master mode and is maintained at 1 while transfer is
underway. It is cleared to 0 once the transfer is completed.
D2
SEIF: Overrun Error Flag Bit
Indicates whether an overrun error has occurred or not.
1 (R):
Error occurred
0 (R):
No error (default)
1 (W):
Reset to 0
0 (W):
Ignored
SEIF is set to 1 when an overrun error occurs. At the same time a receive error interrupt request is sent
to the ITC if SEIE/USI_SIEx register is 1. An overrun error occurs when the previous received data in
the receive data buffer before reading is overwritten with a new received data. SEIF is reset by writing 1.
D1
SRDIF: Receive Buffer Full Flag Bit
Indicates the receive data buffer status.
1 (R):
Data full
0 (R):
No data (default)
1 (W):
Reset to 0
0 (W):
Ignored
SRDIF is set to 1 when data received in the shift register is sent to the receive data buffer (when receiv-
ing is completed), indicating that the data can be read. At the same time a receive buffer full interrupt
request is sent to the ITC if SRDIE/USI_SIEx register is 1. SRDIF is reset by writing 1.
D0
STDIF: Transmit Data Buffer Empty Flag Bit
Indicates the transmit data buffer status.
1 (R):
Empty (default)
0 (R):
Data exists
1 (W):
Reset to 0
0 (W):
Ignored
STDIF is set to 1 when the transmit data written to the transmit data buffer is transferred to the shift
register (when transmission starts), indicating that the next transmit data can be written to. At the same
time a transmit buffer empty interrupt request is sent to the ITC if STDIE/USI_SIEx register is 1.
STDIF is reset by writing 1.