APPENDIX A LIST OF I/O REGISTERS
AP-A-22
Seiko Epson Corporation
S1C17554/564 TECHNICAL MANUAL
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
P4 Port
Chattering
Filter Control
Register
(P4_CHAT)
0x5248
(8 bits)
D7
–
reserved
–
0 when being read.
D6–4 P4CF2[2:0] P4[5:4] chattering filter time
P4CF2[2:0]
Filter time
0
R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
16384/fPCLK
8192/fPCLK
4096/fPCLK
2048/fPCLK
1024/fPCLK
512/fPCLK
256/fPCLK
None
0x0 R/W
D3
–
reserved
–
0 when being read.
D2–0 P4CF1[2:0] P4[3:0] chattering filter time
P4CF1[2:0]
Filter time
0x0 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
16384/fPCLK
8192/fPCLK
4096/fPCLK
2048/fPCLK
1024/fPCLK
512/fPCLK
256/fPCLK
None
P4 Port Input
Enable Register
(P4_IEN)
0x524a
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–0 P4IEN[5:0] P4[5:0] port input enable
1 Enable
0 Disable
0x2f R/W
P5 Port Input
Data Register
(P5_IN)
0x5250
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–0 P5IN[5:0]
P5[5:0] port input data
1 1 (H)
0 0 (L)
×
R
P5 Port Output
Data Register
(P5_OUT)
0x5251
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–0 P5OUT[5:0] P5[5:0] port output data
1 1 (H)
0 0 (L)
0
R/W
P5 Port
Output Enable
Register
(P5_OEN)
0x5252
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–0 P5OEN[5:0] P5[5:0] port output enable
1 Enable
0 Disable
0
R/W
P5 Port Pull-up
Control Register
(P5_PU)
0x5253
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–0 P5PU[5:0]
P5[5:0] port pull-up enable
1 Enable
0 Disable
1
(0x2f)
R/W
P5 Port
Interrupt Mask
Register
(P5_IMSK)
0x5255
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–0 P5IE[5:0]
P5[5:0] port interrupt enable
1 Enable
0 Disable
0
R/W
P5 Port
Interrupt Edge
Select Register
(P5_EDGE)
0x5256
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–0 P5EDGE[5:0] P5[5:0] port interrupt edge select
1 Falling edge 0 Rising edge
0
R/W
P5 Port
Interrupt Flag
Register
(P5_IFLG)
0x5257
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–0 P5IF[5:0]
P5[5:0] port interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
P5 Port
Chattering
Filter Control
Register
(P5_CHAT)
0x5258
(8 bits)
D7
–
reserved
–
0 when being read.
D6–4 P5CF2[2:0] P5[5:4] chattering filter time
P5CF2[2:0]
Filter time
0
R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
16384/fPCLK
8192/fPCLK
4096/fPCLK
2048/fPCLK
1024/fPCLK
512/fPCLK
256/fPCLK
None
0x0 R/W
D3
–
reserved
–
0 when being read.
D2–0 P5CF1[2:0] P5[3:0] chattering filter time
P5CF1[2:0]
Filter time
0x0 R/W
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
16384/fPCLK
8192/fPCLK
4096/fPCLK
2048/fPCLK
1024/fPCLK
512/fPCLK
256/fPCLK
None
P5 Port Input
Enable Register
(P5_IEN)
0x525a
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5–0 P5IEN[5:0] P5[5:0] port input enable
1 Enable
0 Disable
0x2f R/W