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7 CLOCK GENERATOR (CLG)
S1C17554/564 TECHNICAL MANUAL
Seiko Epson Corporation
7-13
D2
Reserved (S1C17554)
IOSCEN: IOSC Enable Bit (S1C17564)
Enables or disables IOSC oscillator operations.
1 (R/W): Enabled (on) (default)
0 (R/W): Disabled (off)
Note: The IOSC oscillator cannot be stopped if the IOSC clock is being used as the system clock.
D1
OSC1EN: OSC1 Enable Bit
Enables or disables OSC1 oscillator operations.
1 (R/W): Enabled (on)
0 (R/W): Disabled (off) (default)
When the system clock is switched to OSC1 immediately after the OSC1 oscillator circuit is turned on,
the OSC1 clock is supplied to the system after the OSC1 clock system supply wait time indicated below
(at a maximum) has elapsed.
OSC1 clock system supply wait time
≤ OSC1 oscillation start time (max.) + OSC1 oscilla-
tion stabilization wait time (256 cycles)
Note: The OSC1 oscillator cannot be stopped if the OSC1 clock is being used as the system clock.
D0
OSC3EN: OSC3 Enable Bit
Enables or disables OSC3 oscillator operations.
1 (R/W): Enabled (on) (default in S1C17554)
0 (R/W): Disabled (off) (default in S1C17564)
Note: The OSC3 oscillator cannot be stopped if the OSC3 clock is being used as the system clock.
Noise Filter Enable Register (CLG_NFEN)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Noise Filter
Enable Register
(CLG_NFEN)
0x5062
(8 bits)
D7–6 –
reserved
–
0 when being read.
D5
OSC1WCE OSC1 wait cycle enable
1 Enable
0 Disable
1
R/W
D4
OSC3WCE OSC3 wait cycle enable
1 Enable
0 Disable
1
R/W
D3–0 –
reserved
–
0 when being read.
D[7:6]
Reserved
D5
OSC1WCE: OSC1 Wait Cycle Enable Bit
Enables or disables the OSC1 oscillation stabilization wait circuit.
1 (R/W): Enabled (default)
0 (R/W): Disabled
When using the internal OSC1 oscillator circuit, enable the OSC1 oscillation stabilization wait circuit
(OSC1WCE = 1). When the OSC1 oscillator circuit is turned on, the OSC1 clock is supplied to the sys-
tem after 256 cycles of oscillation stabilization wait time has elapsed.
When a stabilized external clock is input to the OSC1 pin, setting OSC1WCE to 0 enables the system to
start operating without a stabilization wait time.
D4
OSC3WCE: OSC3 Wait Cycle Enable Bit
Enables or disables the OSC3 oscillation stabilization wait circuit.
1 (R/W): Enabled (default)
0 (R/W): Disabled
When using the internal OSC3 oscillator circuit, enable the OSC3 oscillation stabilization wait circuit
(OSC3WCE = 1). When the OSC3 oscillator circuit is turned on, the OSC3 clock is supplied to the sys-
tem after the oscillation stabilization wait time set using OSC3WT[1:0]/CLG_CTL register has elapsed.
When a stabilized external clock is input to the OSC3 pin, setting OSC3WCE to 0 enables the system to
start operating without a stabilization wait time.
D[3:0]
Reserved